The counter block is used to achieve the customized delay. An additional LUT_0 is used to combine all the 4 PWM output signals with OR logic, and then the output of LUT_0 is designed as the Reset input of Counter_0. Together with both mode0 and mode1 set to 1, this means Counter_0 does not start to count until all PWM output signals shut down. MATCH1 is set with the expected delay value.

The state machine has been implemented with the FSM block as shown in Figure 3-2. Two inputs are used to identify state of S0, where S0 goes down at E0 and rise at E1. E0 is referred to the Counter_0 match1 event, while E1 is from the output of LUT_1, which combines the rising edges of two inner switch PWM signals (PWM1A and PWM1B), which means the CLB output recovers to high state when either of inner PWM signals turn on. Thus, the Karnaugh map can be created for S0 state, as listed in Table 3-2

Based on the Karnaugh map, the FSM equations for S0 can be deduced as

S0=(S0 & ~E0) | (~S0 & E1)