SDAA161 December   2025 TMS320F280025C , TMS320F280037C , TMS320F280039C , TMS320F280041C , TMS320F280049C , TMS320F28379D , TMS320F28379S , TMS320F28P550SG , TMS320F28P550SJ , TMS320F28P650DH , TMS320F28P650DK , TMS320F28P650SH , TMS320F28P650SK

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1Introduction
  5. 2Design Overview
  6. 3CLB Implementation
    1. 3.1 CLB Input Selection
    2. 3.2 Counter and FSM Configuration
    3. 3.3 CLB Output
  7. 4EPWM Configurations
    1. 4.1 Test Results
  8. 5Summary
  9. 6References

2 Design Overview

Figure 1-1 shows the expected EPWM protection behaviors with CLB during positive cycle and negative operation for one phase. The CLB output diagram looks similar to the previous application report, but the way to generate and leverage the CLB output is different.

Expected EPWM Protection Logic With CLB Figure 2-1 Expected EPWM Protection Logic With CLB

Table 2-1 lists the EPWM module and CLB tile assignments for each phase. Since only EPWM1-EPWM4 output can be replaced with the corresponding CLB output due to the peripheral signal multiplexer relationship for CLB for most of C2000 devices, EPWM1,2 and 3 are used for inner switches of three phase respectively.

Table 2-1 EPWM Module and CLB Tile Assignments
Switches Phase 1 Phase 2 Phase 3
S1 EPWM5A EPWM6A EPWM7A
S2 EPWM1B EPWM2B EPWM3B
S3 EPWM1A EPWM2A EPWM3A
S4 EPWM5B EPWM6B EPWM7B
CLB CLB1 CLB2 CLB3