SDAA161 December   2025 TMS320F280025C , TMS320F280037C , TMS320F280039C , TMS320F280041C , TMS320F280049C , TMS320F28379D , TMS320F28379S , TMS320F28P550SG , TMS320F28P550SJ , TMS320F28P650DH , TMS320F28P650DK , TMS320F28P650SH , TMS320F28P650SK

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1Introduction
  5. 2Design Overview
  6. 3CLB Implementation
    1. 3.1 CLB Input Selection
    2. 3.2 Counter and FSM Configuration
    3. 3.3 CLB Output
  7. 4EPWM Configurations
    1. 4.1 Test Results
  8. 5Summary
  9. 6References

3.1 CLB Input Selection

Total 8 CLB input are required for this design, including the input signals (take Phase 1 as example) shown in Table 3-1 .

Table 3-1 CLB Input Signal Selection
in0 in1 in2 in3 in4 in5 in6 in7
S2-EPWM1B S3-EPWM1A S2-EPWM1B (rising edge) S3-EPWM1A (rising edge) S1-EPWM5A S4-EPWM5B S3 EPWM1A_DB
 S2 EPWM1B_DB

In the design, traditional protection response is kept for all EPWM modules, which means all the PWM outputs shut down immediately no matter if there are one-shot or cycle by cycle configurations, triggered by any hardware fault events, or manual shut down (such as software forced trip).