SDAA212 November   2025 AM620-Q1 , AM623 , AM625 , AM625-Q1 , AM62A1-Q1 , AM62A3 , AM62A3-Q1 , AM62A7 , AM62A7-Q1 , AM62D-Q1

 

  1.   1
  2.   Abstract
  3.   How to Use this Document
  4.   Trademarks
  5. 1Digital Audio Formats
    1. 1.1 I2S
    2. 1.2 TDM
  6. 2McASP Overview
  7. 3McASP Connections for AM62x Devices
    1. 3.1 McASP Common Configurations
      1. 3.1.1 McASP as a Clock Controller
        1. 3.1.1.1 Clocks Generated using the AUDIO_EXT_REFCLK AHCLK Source
      2. 3.1.2 McASP as Clock Peripheral
  8. 4McASP Layout Considerations
    1. 4.1 McASP Signals Shared with Bootmode Logic
    2. 4.2 McASP Topology for Multiple Devices in Single Clock Domain
  9. 5McASP Practical Examples
    1. 5.1 Audio Playback using AUDIO_EXT_REFCLK for Two Clock Domains
    2. 5.2 Audio Playback with External Clock Source and McASP SYNC mode
  10. 6Key Audio System Design Takeaways
  11. 7References

5.1 Audio Playback using AUDIO_EXT_REFCLK for Two Clock Domains

Figure 5-1 shows a simple example of how the McASP can use a single internal reference to send and receive audio data across multiple domains. The McASP is operating in asynchronous mode, but because the root clock source is the same for the transmit and receive domain, there is no risk of buffer overrun or underrun (as long as the audio data frame formatting is the same on the input and output).

For this system, an external LVCMOS oscillator (such as the LMK6CE024576) is used to generate an audio clock rate frequency of 24.576 MHz. In this case, the TX and RX domains both have AHCLK configured as externally generated (from AUDIO_EXT_REFCLK0) while ACLK and AFS are configured to be internally generated.

The audio data frame is four audio channels for a single TDM4 stream and, assuming that the word depth is 32 bits, then the bit clock can be calculated based on the product of 4 channels of 32 bit words that are sampled at 48kHz = 4*32*48,000 = 6.144 MHz.

ADC DAC Audio Playback Figure 5-1 ADC DAC Audio Playback