SDAA212 November   2025 AM620-Q1 , AM623 , AM625 , AM625-Q1 , AM62A1-Q1 , AM62A3 , AM62A3-Q1 , AM62A7 , AM62A7-Q1 , AM62D-Q1

 

  1.   1
  2.   Abstract
  3.   How to Use this Document
  4.   Trademarks
  5. 1Digital Audio Formats
    1. 1.1 I2S
    2. 1.2 TDM
  6. 2McASP Overview
  7. 3McASP Connections for AM62x Devices
    1. 3.1 McASP Common Configurations
      1. 3.1.1 McASP as a Clock Controller
        1. 3.1.1.1 Clocks Generated using the AUDIO_EXT_REFCLK AHCLK Source
      2. 3.1.2 McASP as Clock Peripheral
  8. 4McASP Layout Considerations
    1. 4.1 McASP Signals Shared with Bootmode Logic
    2. 4.2 McASP Topology for Multiple Devices in Single Clock Domain
  9. 5McASP Practical Examples
    1. 5.1 Audio Playback using AUDIO_EXT_REFCLK for Two Clock Domains
    2. 5.2 Audio Playback with External Clock Source and McASP SYNC mode
  10. 6Key Audio System Design Takeaways
  11. 7References

6 Key Audio System Design Takeaways

  • The McASP has two modes of operation for clock synchronization:
    • Sync mode: where the ACLKX and AFSX signals are internally routed to ACLKR and AFSR and all audio data is sent and received with a single clock domain.
    • Asynchronous mode: The TX and RX clock domains are independent of each other and the audio data clock domains are determined by the serializer IO direction.

  • Multizone audio systems ideally have one clock reference for all generated bit clocks and frame syncs in order to avoid audio data buffering issues. For the AM62x devices, the clock reference must be provided by an external source.
    • Either the McASPs need to be configured to internally reference an AUDIO_EXT_REFCLK input or they need to have the bit clock and frame syncs configured to be externally generated.
      • If the external source does not have a device level high-frequency reference, then the bit clock must also be routed to an AUDIO_EXT_REFCLK input to enable other McASP instances with the same reference.

  • Carefully review all bootmode signals that are shared with McASP signals to ensure that there aren't any unnecessary trace stubs introduced on the clock or data signal lines.
  • For clock and data signals that are shared across multiple devices, ensure that the layout topology does not impact the performance of the signal.
    • Always simulate the signal with the proposed layout topology to ensure the reliability and integrity of the audio data transfers.