SDAA212 November   2025 AM620-Q1 , AM623 , AM625 , AM625-Q1 , AM62A1-Q1 , AM62A3 , AM62A3-Q1 , AM62A7 , AM62A7-Q1 , AM62D-Q1

 

  1.   1
  2.   Abstract
  3.   How to Use this Document
  4.   Trademarks
  5. 1Digital Audio Formats
    1. 1.1 I2S
    2. 1.2 TDM
  6. 2McASP Overview
  7. 3McASP Connections for AM62x Devices
    1. 3.1 McASP Common Configurations
      1. 3.1.1 McASP as a Clock Controller
        1. 3.1.1.1 Clocks Generated using the AUDIO_EXT_REFCLK AHCLK Source
      2. 3.1.2 McASP as Clock Peripheral
  8. 4McASP Layout Considerations
    1. 4.1 McASP Signals Shared with Bootmode Logic
    2. 4.2 McASP Topology for Multiple Devices in Single Clock Domain
  9. 5McASP Practical Examples
    1. 5.1 Audio Playback using AUDIO_EXT_REFCLK for Two Clock Domains
    2. 5.2 Audio Playback with External Clock Source and McASP SYNC mode
  10. 6Key Audio System Design Takeaways
  11. 7References

3.1 McASP Common Configurations

The McASP bit clock (ACLK) and frame sync (AFS) are both bidirectional such that the McASP can either be the clock controller or clock peripheral. The following sections detail all the available options for each clocking configuration.

Table 3-2 lists the most common use cases for configuring McASP. The AM62x SoCs have many options for generating, sourcing, and receiving clocks for the audio data frame formatting.

Note: For bit clock and frame sync, internally generated refers to internally referenced signals that are output at the SoC level for McASP clock controller applications while externally generated means that the signals are configured as inputs at the SoC level for McASP clock peripheral applications.
Table 3-1 McASP Use Case Matrix
Description AHCLK Bit Clock Frame Sync McASP Example
McASP clock controller with internal audio PLL reference AM62x Devices do not feature an internal audio PLL reference for generating audio bit clock and frame sync frequencies.
McASP clock controller with external AUXCLK reference AM62x Devices do not feature an option to route an external clock source to the McASP AUXCLK
McASP clock controller with external AHCLK reference Externally Generated Internally Generated Internally Generated Section 3.1.1.1 Figure 5-1
McASP clock peripheral Externally Generated Externally Generated Section 3.1.2 Figure 5-2

Figure 3-2 shows a more detailed view of the available options.

McASP Detailed Overview Figure 3-2 McASP Detailed Overview