Figure 5-2 shows a simple example of how a McASP can send and receive audio data with only a single clock reference. The McASP is operating in synchronous mode meaning that the transmit bit clock and frame sync are internally routed to the receive bit clock and frame sync, respectively. The internal routing of the RX domain allows for a single McASP instance to have serializers for input and output of audio data as long as all audio data streams have the same frame formatting.

For this system, a 4-channel codec is the clock controller for both the bit clock and frame sync. The TX and RX domains are in SYNC mode and have ACLK and AFS configured to be externally generated. If bit clock and frame sync are externally generated, the AHCLK is not required for operation and can be considered a "don't care" value.

The audio data frame is four audio channels for a single TDM4 stream and, assuming that the word depth is 32 bits, then the bit clock can be calculated based on the product of 4 channels of 32 bit words that are sampled at 48 kHz = 4*32*48,000 = 6.144 MHz.

Figure 5-2 Codec Playback with McASP as Clock Peripheral in Sync Mode