SDAA228 September   2026 MSPM33C321A

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1 Introduction
    1. 1.1 Terminology
  5. 2 NONMAIN Architecture
    1. 2.1 MSPM33 Family Overview
    2. 2.2 NONMAIN Configuration Overview
    3. 2.3 NONMAIN Memory
  6. 3 NONMAIN Configuration
    1. 3.1 BCR Configuration
      1. 3.1.1 BCR Configuration ID
      2. 3.1.2 Serial Wire Debug (SWD) Policy
        1. 3.1.2.1 Access Policy
        2. 3.1.2.2 Debug Policy
          1. 3.1.2.2.1 SHA2-256 Password Example
        3. 3.1.2.3 Mass Erase and Factory Reset Policy
      3. 3.1.3 Flash Security Configuration
        1. 3.1.3.1 MAIN Flash Security Configuration
        2. 3.1.3.2 DATA Flash Security Configuration
        3. 3.1.3.3 NONMAIN Flash Static Write Protection
      4. 3.1.4 SYSPLL Configuration During Boot
      5. 3.1.5 Customer Secure Code (CSC)
        1. 3.1.5.1 CSC Policy
        2. 3.1.5.2 Flash Bank Swap Policy
        3. 3.1.5.3 Debug Hold
      6. 3.1.6 Fast Boot Mode
      7. 3.1.7 Application Digest Check
        1. 3.1.7.1 CRC32 Digest Check Example
        2. 3.1.7.2 SHA2-256 Digest Check Example
      8. 3.1.8 BSL Policy
      9. 3.1.9 BCR Checksum
        1. 3.1.9.1 CRC Check Fail Handling
    2. 3.2 BSL Configuration
      1. 3.2.1 BSL Configuration ID
      2. 3.2.2 Invoke Pin Configuration
      3. 3.2.3 ROM-Based Communication Interface
        1. 3.2.3.1 UART Interface
        2. 3.2.3.2 I2C Interface
        3. 3.2.3.3 CAN Interface
      4. 3.2.4 BSL Security Configuration
        1. 3.2.4.1 Access Password
        2. 3.2.4.2 Read-Out Feature
        3. 3.2.4.3 Alert Feature
        4. 3.2.4.4 Application Integrity Check
      5. 3.2.5 BSL Checksum
        1. 3.2.5.1 CRC Check Fail Handling
  7. 4 NONMAIN Configuration With SysConfig
    1. 4.1 SysConfig Introduction
    2. 4.2 BCR Configuration With SysConfig
      1. 4.2.1 Password Configuration
      2. 4.2.2 SYSPLL Configuration
      3. 4.2.3 Flash Security Configuration
      4. 4.2.4 Application Digest Check
      5. 4.2.5 Other BCR Configurations
    3. 4.3 BSL Configuration With SysConfig
      1. 4.3.1 BSL Access Password
      2. 4.3.2 BSL Invoke Pin Configuration
      3. 4.3.3 BSL Communication Interface
      4. 4.3.4 Other BCR Configurations
  8. 5 NONMAIN Configuration in Application Code
  9. 6 NONMAIN Operation With IDE Tool
    1. 6.1 NONMAIN Configuration Files
    2. 6.2 Project Erase Property
    3. 6.3 Password-Protected Debug
  10. 7 NONMAIN Operation With Programmer Tool
    1. 7.1 NONMAIN Operation With UniFlash
    2. 7.2 NONMAIN Operation With J-Flash
  11. 8 Frequently Asked Questions (FAQs)
    1. 8.1 MCU Locked State Analysis
      1. 8.1.1 Hardware Issue Analysis
        1. 8.1.1.1 Hardware Circuit Design
        2. 8.1.1.2 Debugger Connection
        3. 8.1.1.3 External Reset Signal
      2. 8.1.2 Software Issue Analysis
        1. 8.1.2.1 CPU Enters a Fault State
        2. 8.1.2.2 BCR Configuration
        3. 8.1.2.3 Low Power Mode (STOP or STANDBY)
        4. 8.1.2.4 SHUTDOWN IO State
        5. 8.1.2.5 SWD IO Function
        6. 8.1.2.6 WDT or IWDT Reset
        7. 8.1.2.7 Software POR or BOOTRST
    2. 8.2 Unlock the MSPM33 Device
      1. 8.2.1 Force MCU to Enter BSL Mode
      2. 8.2.2 Send BSL Command
      3. 8.2.3 Generate DSSM Command
    3. 8.3 Debug Error Overview
      1. 8.3.1 No Error Code: DAP Connection Error
      2. 8.3.2 No Error Code: Connection to the MSPM33 Core Failed
      3. 8.3.3 Error – 6305: PRSC Module Failed to Write a Routine Register
      4. 8.3.4 Error – 260: An Attempt to Connect to the XDS110 Failed
      5. 8.3.5 Error – 261: Invalid Response From the XDS110
      6. 8.3.6 Error – 615: Target Fails to Identify a Correctly Formatted SWD Header
      7. 8.3.7 Error – 1001: Requested Operation is Not Supported on This Device
      8. 8.3.8 Error – 2131: Unable to Access Device Register
    4. 8.4 MSPM33 Boot Diagnostic
  12. 9 Summary
  13. 10References

3.1.4 SYSPLL Configuration During Boot

With the default configuration, ROM boot is executed with a 32MHz MCLK, sourced by the SYSOSC, and no SYSPLL. To speed up the boot process, the user can configure a SYSPLL as well as the clock source. The user can configure the following settings:

  • SYSPLL predivider (PDIV) and SYSPLL feedback divider (QDIV)
  • Clock source selection – SYSOSC (32MHz) or HFXT (20MHz or 40MHz)

Set the SYSPLL configuration using the BOOTCLK0 and BOOTCLK1 fields in the NONMAIN flash memory.