SDAA565 October   2026 AM2431 , AM2432 , AM2434 , AM6411 , AM6412 , AM6422 , AM6441 , AM6442

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1Introduction
  5. 2Hardware Architecture
    1. 2.1 EVM Configuration
    2. 2.2 APS6408L PSRAM Device
      1. 2.2.1 OSPI PSRAM Configurations
  6. 3Software Architecture
  7. 4Implementation Guide
    1. 4.1 Prerequisites
    2. 4.2 Example Applications
      1. 4.2.1 Secondary Bootloaders
        1. 4.2.1.1 SBL OSPI PSRAM
        2. 4.2.1.2 SBL SD PSRAM
      2. 4.2.2 OSPI PSRAM I/O
      3. 4.2.3 Hello World with Code Execution from OSPI PSRAM
    3. 4.3 Integrating OSPI PSRAM into Custom Applications
  8. 5Performance Analysis and Benchmarks
    1. 5.1 Read and Write Throughput
    2. 5.2 Simulated Application Benchmarks
      1. 5.2.1 XIP Benchmark
      2. 5.2.2 On-Chip Memory Benchmark
    3. 5.3 PROFINET Benchmarks
      1. 5.3.1 Performance Degradation using Fast Startup Time
      2. 5.3.2 Performance Degradation using CPU Load
  9. 6Summary
  10. 7References

5.3.1 Performance Degradation using Fast Startup Time

Example used: PROFINET Device Demo

To depict the performance degradation, only the text and read-only data were moved to the memory under test.

Table 5-7 shows the memory configurations used for profiling Fast Startup (FSU) times:

Table 5-7 Memory Layout Configurations for Fast Startup Time
Memory SectionsDDR CaseOSPI PSRAM CaseOSPI NOR Flash Case
VectorsTCMATCMATCMA
HWI & TCM textTCMATCMATCMA
StackOCRAMOCRAMOCRAM
RW DataOCRAMOCRAMOCRAM
BSSOCRAMOCRAMOCRAM
Startup CodeOCRAMOCRAMOCRAM
ICSS Packet BufferOCRAMOCRAMOCRAM
Sys MemOCRAMOCRAMOCRAM
Text (803KB)DDRPSRAMFlash
RO Data (66KB)DDRPSRAMFlash

FSU time is obtained by measuring the difference between two hardware signals. The first signal is measured after the device has been powered on. For this, the MCU_PORz signal is used. The second signal is measured after the first successful PROFINET cyclic data exchange. The time between the two signals going high is the FSU time. The Delta time shown is the FSU time minus SBL time and indicates the time taken for the RO data and the text sections to be executed from DDR/OSPI PSRAM/OSPI NOR Flash.

The SBL times vary significantly across memory configurations due to differences in data transfer requirements and OSPI controller reconfiguration overhead. For DDR execution, the SBL transfers application sections from OSPI NOR Flash to DDR, requiring 103ms. For OSPI NOR Flash execution at 25MHz DDR, sections remain in OSPI NOR Flash after initial programming, reducing SBL time to 55ms because no transfer occurs. OSPI NOR Flash execution at 166MHz DDR adds PHY tuning algorithm overhead of approximately 25ms, resulting in an 81ms SBL time.

OSPI PSRAM execution exhibits the longest SBL time of 194ms due to the volatile nature of OSPI PSRAM combined with the shared OSPI controller architecture. The SBL must load sections into a temporary OCRAM buffer, strip the section headers, and manually transfer the contents to the OSPI PSRAM, frequently toggling the multiplexing switch and reinitializing OSPI drivers throughout the process. The AM64x device contains only one OSPI controller with a single set of configuration registers, and the sections have to be transferred from the OSPI NOR Flash to the OSPI PSRAM. As a result, the OSPI PSRAM SBL time is inherently higher than that of the other configurations.

Table 5-8 shows the Fast Startup times obtained using the above setup:

Table 5-8 Performance Metrics for Fast Startup Time
Time TakenDDR

OSPI PSRAM

(25MHz DDR)

OSPI NOR Flash

(25MHz DDR)

OSPI NOR Flash

(166MHz DDR)

Rest of the ApplicationOCRAM, TCMOCRAM, TCMOCRAM, TCMOCRAM, TCM
RO Data, TextDDRPSRAMFlashFlash
SBL (in ms)1031945581
FSU (in ms)519867735701
Delta (FSU-SBL)416673680620