SDAA565 October   2026 AM2431 , AM2432 , AM2434 , AM6411 , AM6412 , AM6422 , AM6441 , AM6442

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1Introduction
  5. 2Hardware Architecture
    1. 2.1 EVM Configuration
    2. 2.2 APS6408L PSRAM Device
      1. 2.2.1 OSPI PSRAM Configurations
  6. 3Software Architecture
  7. 4Implementation Guide
    1. 4.1 Prerequisites
    2. 4.2 Example Applications
      1. 4.2.1 Secondary Bootloaders
        1. 4.2.1.1 SBL OSPI PSRAM
        2. 4.2.1.2 SBL SD PSRAM
      2. 4.2.2 OSPI PSRAM I/O
      3. 4.2.3 Hello World with Code Execution from OSPI PSRAM
    3. 4.3 Integrating OSPI PSRAM into Custom Applications
  8. 5Performance Analysis and Benchmarks
    1. 5.1 Read and Write Throughput
    2. 5.2 Simulated Application Benchmarks
      1. 5.2.1 XIP Benchmark
      2. 5.2.2 On-Chip Memory Benchmark
    3. 5.3 PROFINET Benchmarks
      1. 5.3.1 Performance Degradation using Fast Startup Time
      2. 5.3.2 Performance Degradation using CPU Load
  9. 6Summary
  10. 7References

4.2.1.1 SBL OSPI PSRAM

This secondary bootloader enables code execution from OSPI PSRAM by transferring the XIP image (the image ending with the .mcelf_xip extension) from the OSPI NOR Flash to the OSPI PSRAM. By dynamically switching between the OSPI NOR Flash and OSPI PSRAM, this example also demonstrates how different sections are loaded to different memory regions such as the OSPI PSRAM.

Perform the following steps to enable code execution from OSPI PSRAM using SBL OSPI PSRAM:

  1. After building the example, use the offsets specified in default_sbl_ospi_psram.cfg to flash the .mcelf.hs_fs and the .mcelf_xip images.
  2. After flashing the binaries in UART boot mode, power off the EVM, switch to the OSPI boot mode, and power on the EVM.
Note: Use the offsets specified in the .cfg file, because the offset at which the XIP image is written must match the XIP_FLASH_OFFSET defined in the main.c file of the SBL OSPI PSRAM example.
When the OSPI_SW_SEL is driven high, the following memory layout of the OSPI PSRAM is visible to the CPU in DAC mode:
OSPI PSRAM Memory LayoutFigure 4-1 OSPI PSRAM Memory Layout
When the OSPI_SW_SEL is driven low, the following memory layout of the OSPI NOR Flash is visible to the CPU in DAC mode:
OSPI NOR Flash Memory LayoutFigure 4-2 OSPI NOR Flash Memory Layout
Note: The memory region defined for OSPI PSRAM must always be marked as "Cached" and the memory region for OSPI NOR Flash must be marked as "Strongly Ordered" if Flash writes are being performed in the memory region.