SDAA565 October   2026 AM2431 , AM2432 , AM2434 , AM6411 , AM6412 , AM6422 , AM6441 , AM6442

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1Introduction
  5. 2Hardware Architecture
    1. 2.1 EVM Configuration
    2. 2.2 APS6408L PSRAM Device
      1. 2.2.1 OSPI PSRAM Configurations
  6. 3Software Architecture
  7. 4Implementation Guide
    1. 4.1 Prerequisites
    2. 4.2 Example Applications
      1. 4.2.1 Secondary Bootloaders
        1. 4.2.1.1 SBL OSPI PSRAM
        2. 4.2.1.2 SBL SD PSRAM
      2. 4.2.2 OSPI PSRAM I/O
      3. 4.2.3 Hello World with Code Execution from OSPI PSRAM
    3. 4.3 Integrating OSPI PSRAM into Custom Applications
  8. 5Performance Analysis and Benchmarks
    1. 5.1 Read and Write Throughput
    2. 5.2 Simulated Application Benchmarks
      1. 5.2.1 XIP Benchmark
      2. 5.2.2 On-Chip Memory Benchmark
    3. 5.3 PROFINET Benchmarks
      1. 5.3.1 Performance Degradation using Fast Startup Time
      2. 5.3.2 Performance Degradation using CPU Load
  9. 6Summary
  10. 7References

4.2.2 OSPI PSRAM I/O

This example demonstrates the communication between the OSPI controller present in the SoC and the OSPI PSRAM. This application writes 512KB of randomly generated data into the OSPI PSRAM, and the same data is read back and compared. If there is no mismatch between the data sent and received, the read and write throughputs are then calculated.

This example can be run by using SBL NULL, then loading and running the .out file through Code Composer Studio™ (CCS). This application can also be run with SBL OSPI PSRAM or SBL SD PSRAM by following the steps described in Section 4.2.1.1 and Section 4.2.1.2.