SDAA565 October   2026 AM2431 , AM2432 , AM2434 , AM6411 , AM6412 , AM6422 , AM6441 , AM6442

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1Introduction
  5. 2Hardware Architecture
    1. 2.1 EVM Configuration
    2. 2.2 APS6408L PSRAM Device
      1. 2.2.1 OSPI PSRAM Configurations
  6. 3Software Architecture
  7. 4Implementation Guide
    1. 4.1 Prerequisites
    2. 4.2 Example Applications
      1. 4.2.1 Secondary Bootloaders
        1. 4.2.1.1 SBL OSPI PSRAM
        2. 4.2.1.2 SBL SD PSRAM
      2. 4.2.2 OSPI PSRAM I/O
      3. 4.2.3 Hello World with Code Execution from OSPI PSRAM
    3. 4.3 Integrating OSPI PSRAM into Custom Applications
  8. 5Performance Analysis and Benchmarks
    1. 5.1 Read and Write Throughput
    2. 5.2 Simulated Application Benchmarks
      1. 5.2.1 XIP Benchmark
      2. 5.2.2 On-Chip Memory Benchmark
    3. 5.3 PROFINET Benchmarks
      1. 5.3.1 Performance Degradation using Fast Startup Time
      2. 5.3.2 Performance Degradation using CPU Load
  9. 6Summary
  10. 7References

2.1 EVM Configuration

The OSPI PSRAM from AP Memory is not available on the default TMDS64EVM, and is only available on the modified TMDS64EVM that follows the PROC101E1_OSPI schematic. The modification made to the default EVM is the addition of the TS3DDR3812RUAR high-speed switch that multiplexes the OSPI signals between the OSPI NOR Flash and OSPI PSRAM.

The OSPI_SW_SEL signal is driven by pin 23 of the TCA6424A I/O expander, which is controlled over I2C1. When the OSPI_SW_SEL is asserted (driven high), the OSPI signals are routed to the OSPI PSRAM, enabling the SoC to communicate with the OSPI PSRAM. By default, the OSPI_SW_SEL is low, so that the OSPI signals are routed to the OSPI NOR Flash, enabling the default boot from OSPI NOR Flash.

OSPI Signal Routing Through High-Speed SwitchFigure 2-1 OSPI Signal Routing Through High-Speed Switch