SDAA565 October   2026 AM2431 , AM2432 , AM2434 , AM6411 , AM6412 , AM6422 , AM6441 , AM6442

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1Introduction
  5. 2Hardware Architecture
    1. 2.1 EVM Configuration
    2. 2.2 APS6408L PSRAM Device
      1. 2.2.1 OSPI PSRAM Configurations
  6. 3Software Architecture
  7. 4Implementation Guide
    1. 4.1 Prerequisites
    2. 4.2 Example Applications
      1. 4.2.1 Secondary Bootloaders
        1. 4.2.1.1 SBL OSPI PSRAM
        2. 4.2.1.2 SBL SD PSRAM
      2. 4.2.2 OSPI PSRAM I/O
      3. 4.2.3 Hello World with Code Execution from OSPI PSRAM
    3. 4.3 Integrating OSPI PSRAM into Custom Applications
  8. 5Performance Analysis and Benchmarks
    1. 5.1 Read and Write Throughput
    2. 5.2 Simulated Application Benchmarks
      1. 5.2.1 XIP Benchmark
      2. 5.2.2 On-Chip Memory Benchmark
    3. 5.3 PROFINET Benchmarks
      1. 5.3.1 Performance Degradation using Fast Startup Time
      2. 5.3.2 Performance Degradation using CPU Load
  9. 6Summary
  10. 7References

5.2.1 XIP Benchmark

Example used: XIP Benchmark

Table 5-3 shows the performance metrics obtained for the XIP benchmark example:

Table 5-3 Performance Metrics for XIP Benchmark
Memory DevicesOCRAMDDR

OSPI

PSRAM

(25MHz DDR)

OSPI

NOR Flash

(25MHz DDR)

MPU Region Configuration
Region AttributesCachedCachedCachedCached
Sections
RO Data, TextOCRAMDDRPSRAMFlash
Rest of the ApplicationOCRAMOCRAMOCRAMOCRAM
Benchmarks

CPU Stats

(Number of CPU cycles used)

FIRMin24072240722407224072
Max28447381037497893792
Avg24512255102965431026
MEMCPYMin1565156515651565
Max2010304052038608
Avg1614172019322275

Relative Degradation with respect to OCRAM

(Max cycles)

FIR1xApproximately 1.3xApproximately 2.6xApproximately 3.3x
MEMCPY1xApproximately 1.5xApproximately 2.6xApproximately 4.3x

Relative Degradation with respect to OCRAM

(Average cycles)

FIR1xApproximately 1xApproximately 1.2xApproximately 1.3x
MEMCPY1xApproximately 1.1xApproximately 1.2xApproximately 1.4x

The XIP Benchmark measures how the memory that holds the code and read-only data affects a CPU-bound workload running in XIP mode. The SoC boots and runs the application on the R5F core under FreeRTOS™. The application executes two functions: FIR and MEMCPY.

The linker command file places the text and read-only (RO) data sections in the memory under test, and the rest of the application remains in OCRAM. In the baseline case, all sections are placed in OCRAM. Each function is run a total of 10 times and the worst-case, best-case, and average-case performance is printed on the UART terminal in units of CPU cycles. The maximum (which comes from the cold-cache first run) and average number of CPU cycles for OCRAM are taken as the baseline and the relative performance degradation are then calculated for each test case.