SGLS154F November   2000  – September 2025 TLV3701-Q1 , TLV3702-Q1

PRODUCTION DATA  

  1.   1
  2. Features
  3. Applications
  4. Description
  5. Device Comparison Table
  6. Pin Configuration and Functions
    1.     Pin Configuration: TLV3701
    2.     Pin Configurations: TLV3702
  7. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 Dissipation Rating Table
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Electrical Characteristics
    5. 6.5 Switching Characteristics
    6. 6.6 Typical Characteristics
  8. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagrams
    3. 7.3 Feature Description
    4. 7.4 Device Functional Modes
      1. 7.4.1 Inputs
        1. 7.4.1.1 Operating Common-Mode Ranges
        2. 7.4.1.2 Fail-Safe Inputs
        3. 7.4.1.3 Unused Inputs
      2. 7.4.2 Internal Hysteresis
      3. 7.4.3 Outputs
        1. 7.4.3.1 Push-Pull Output
      4. 7.4.4 ESD Protection
        1. 7.4.4.1 Inputs
        2. 7.4.4.2 Outputs
      5. 7.4.5 Power-On Reset (POR)
      6. 7.4.6 Reverse Battery Protection
  9. Device and Documentation Support
    1. 8.1 Receiving Notification of Documentation Updates
    2. 8.2 Support Resources
    3. 8.3 Electrostatic Discharge Caution
    4. 8.4 Glossary
  10. Revision History
  11. 10Mechanical, Packaging, and Orderable Information

Inputs

The fail-safe inputs incorporates internal ESD protection circuits on all pins. The fail-safe inputs have ESD protection from each pin to (V-) which allows these pins to exceed the supply voltage (V+) up to 16V. If input voltages are to exceed 16V, an external clamp is required. Likewise, negative voltages on the inputs are ESD clamped to (V-) and must be limited to less than -0.1V.

If the inputs are to be connected to a low impedance source such as a power supply or buffered reference line, add a current-limiting resistor in series with the input to limit any transient currents if the clamps conduct. The current is be limited to 10mA or less. This series resistance can be part of any resistive input dividers or networks.