SLAA988A December   2020  – January 2022 TAS2563

 

  1.   Trademarks
  2. 1Layout Guidelines
    1. 1.1  Typical Application Circuit
    2. 1.2  VBAT
    3. 1.3  DREG
    4. 1.4  GREG
    5. 1.5  PVDD and VBST
    6. 1.6  VDD
    7. 1.7  IOVDD
    8. 1.8  Output Pins
    9. 1.9  Sense Pins
    10. 1.10 Digital Portion
    11. 1.11 Ground Planes
  3. 2Schematic
    1. 2.1 Recommended External Components
  4. 3Decoupling Capacitors
  5. 4Revision History

Digital Portion

The TAS2563 device involves digital and analog activity. Care must be taken when routing the different signals since it may result in noise issues, especially from the digital lines to the analog portion.

The digital lines can reach frequencies up to 1 MHz for the I2C lines in Fast-Mode Plus and up to 50 MHz for the I2S lines. This high-frequency content can affect the performance of the analog signals. For measurement purposes, the digital noise level may affect the scope captures or a THD+N measurement.

GUID-20201210-CA0I-MMKJ-CGVK-MD0NHFS06PLT-low.pngFigure 1-12 Digital Conections