SLAA988A December   2020  – January 2022 TAS2563

 

  1.   Trademarks
  2. 1Layout Guidelines
    1. 1.1  Typical Application Circuit
    2. 1.2  VBAT
    3. 1.3  DREG
    4. 1.4  GREG
    5. 1.5  PVDD and VBST
    6. 1.6  VDD
    7. 1.7  IOVDD
    8. 1.8  Output Pins
    9. 1.9  Sense Pins
    10. 1.10 Digital Portion
    11. 1.11 Ground Planes
  3. 2Schematic
    1. 2.1 Recommended External Components
  4. 3Decoupling Capacitors
  5. 4Revision History

VDD

VDD is the analog and digital power supply input. Similar to the VBAT pin, this power pin requires a decoupling capacitor. A minimum of 4.7-µF capacitor is suggested to bypass VDD to GND. See the Decoupling Capacitors section for details.

This pin requires having a maximum parasitic inductance of 200 pH.

GUID-20201210-CA0I-RZZR-XSLB-K5VXMJSJBH1C-low.pngFigure 1-8 VDD Connection