SLAAE88D December   2022  – September 2025 MSPM0C1105 , MSPM0C1106 , MSPM0G1105 , MSPM0G1106 , MSPM0G1107 , MSPM0G1505 , MSPM0G1506 , MSPM0G1507 , MSPM0G3105 , MSPM0G3106 , MSPM0G3107 , MSPM0G3505 , MSPM0G3506 , MSPM0G3507 , MSPM0H3216 , MSPM0L1105 , MSPM0L1106 , MSPM0L1227 , MSPM0L1227-Q1 , MSPM0L1228 , MSPM0L1228-Q1 , MSPM0L1303 , MSPM0L1304 , MSPM0L1304-Q1 , MSPM0L1305 , MSPM0L1305-Q1 , MSPM0L1306 , MSPM0L1306-Q1 , MSPM0L1343 , MSPM0L1344 , MSPM0L1345 , MSPM0L1346 , MSPM0L2227 , MSPM0L2227-Q1 , MSPM0L2228 , MSPM0L2228-Q1

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1 Introduction
    1. 1.1 Bootloader Concept
    2. 1.2 MSPM0 Bootloader Structure
      1. 1.2.1 ROM-Based BSL
      2. 1.2.2 ROM-Based BSL With Flash-Based Plug-In Interface
      3. 1.2.3 Flash-Based Secondary BSL
    3. 1.3 MSPM0 BSL Features and Demos Summary
  5. 2BSL Host Implementation Summary
  6. 3BSL Configuration in Non-Main (Configuration NVM)
    1. 3.1 Non-Main Introduction
    2. 3.2 Example – Disable PA18 BSL Invoke Pin With Sysconfig
  7. 4Bootloader Host
    1. 4.1 MCU Host Code Introduction
      1. 4.1.1 Hardware Connection
      2. 4.1.2 TXT to Header File Conversion
      3. 4.1.3 Step-by-Step Using the Demo
    2. 4.2 PC Host Example
      1. 4.2.1 Prepare the Image File and Password File
      2. 4.2.2 Steps to Using the GUI
  8. 5Bootloader Target
    1. 5.1 Default ROM-Based BSL
      1. 5.1.1 UART Interface
      2. 5.1.2 I2C Interface
    2. 5.2 Flash-Based Plug-In Interface Demos
      1. 5.2.1 UART Interface
        1. 5.2.1.1 Step by Step Using the Demo
        2. 5.2.1.2 How to Debug the Plug-In Interface Code
      2. 5.2.2 I2C Interface
      3. 5.2.3 SPI Interface
      4. 5.2.4 CAN Interface
    3. 5.3 Secondary BSL Demo
      1. 5.3.1 Flash-Based Secondary BSL Start From 0x1000
      2. 5.3.2 Flash-Based Secondary BSL Start From 0x0000
        1. 5.3.2.1 Flash-Based 0x0 Address BSL Demo for MSPM0C
        2. 5.3.2.2 Live Firmware Update
  9. 6Common Questions
    1. 6.1 Linker File Modification
    2. 6.2 Factory Reset by CCS to Recover Device
  10. 7References
  11. 8Revision History

1.2 MSPM0 Bootloader Structure

There are three kind of Bootloader designs provided with MSPM0 devices: ROM-based BSL, ROM-based BSL with flash based plug-in interface and flash-based secondary BSL. Just choose one of the three designs based on the application's requirement. Both of the designs use the same invoke mode (general-purpose input/output (GPIO) invoke, blank-device detection and software invoke). There are some parameters that need to be configured in the NON-MAIN flash. For more details, see Section 3.

Table 1-1 MSPM0L and MSPM0G BSL Designs Summary
BSL Designs ROM Cost Flash Cost (By default) Interface Pins Used With Hardware Invoke Pins Used With Software Invoke Using Case
ROM Based BSL 5K N/A UART 4 2 Need to follow TI's protocol and the setting with UART/I2C
I2C 4 2
ROM Based BSL with Plug-In interface 5K (just used the BSL Core section) ~ 1.6K UART 4 2 Need to follow TI's protocol, for the interface level are totally open source.
~ 1.3K I2C 4 2
~ 1.6K SPI 6 4
~ 6K CAN 4 2
Flash Based Secondary BSL N/A ~ 5K UART 4 2 Totally open source.
~ 5K I2C 4 2
~ 5K SPI 6 4
~ 9K CAN 4 2
Note: Hardware invoke needs two more pins than software invoke, the pins are reset pin and GPIO invoke pin.
Table 1-2 MSPM0C/H Design Summary
BSL Design Flash Cost Interface Pins Used With Hardware Invoke Pins Used With Software Invoke Using Case
Flash Based BSL ~ 4K UART 4 2 Totally open source.
~ 4K I2C 4 2
Note: The flash cost is with limited features: Mass Erase, Get device Identity and Program. Other features can be enabled in the code.

Figure 1-2 shows the structure of BSL in MSPM0.

BSL Structure in MSPM0 Figure 1-2 BSL Structure in MSPM0