The structure of CAN-SPI bridge with protocol transmission can be seen in Figure 2-3 and Figure 2-4. Figure 2-3 is for SPI master and Figure 2-4 is for SPI slave. The CAN- SPI bridge can be divided into four independent tasks: receive from the SPI, receive from the CAN, transmit through the CAN, transmit through the SPI. Two FIFOs implement bidirectional message transfer and message caching.

The structure of the CAN- SPI bridge with transparent transmission is shown in Figure 2-3 and Figure 2-5. Figure 2-3 is for the SPI master and Figure 2-5 is for the SPI slave. A timer interrupt is added to the CAN-SPI (SPI target) bridge to detect the timeout as the end of one packet.

Both the SPI and CAN reception are set to interrupt triggers so that messages can be received in time. When entering an interrupt, the message is first received through getXXXRxMsg().

For the CAN, a CAN frame is a fixed format. MSPM0 supports classic CAN or CANFD. Figure 2-2 shows the CANFD frame. The example in this document can define 0/1/4 bytes of additional ID in the data area for protocol transmission, which is listed in Table 2-1.

For SPI protocol transmission, messages are identified based on serial frame information. The SPI message format is listed in Table 2-2.

The header is a fixed hex number combined with 0x55 0xAA, which means the start of the group. The ID area occupies four bytes as default to match the CAN ID, which can be configured as one byte or doesn't exist. The data length area occupies one byte. After the data length area, a certain length of data is followed. This format is provided as an example. Users can modify the format according to application requirements.

Note that the SPI is a communication method where the SPI master controls the transmission and reception. In general, the SPI slave cannot initiate communication. For SPI slave-to-master communication, SPI slave pulls down the IO when messages must be sent, as shown in Figure 2-4 . The SPI master initiates the SPI read command in IO interrupt when IO is detected low, as shown in Figure 2-3.

For SPI transparent transmission, messages are identified when timeout occurs (on the SPI slave), as shown in Figure 2-4. All bytes are regards as pure data. Default value is loaded for packet information (for example ID).

After receiving the message, processXXXRxMsg() converts the format of the message and stores the message in the FIFO as a new element. The format of FIFO element can be seen in Figure 2-6. In the format of the FIFO element, there are origin_id, destination_id, data length and data functions. Users can also change the message items according to application requirements. In addition, this scheme also checks whether the FIFO is full for overload control. Users can add overload control actions as requirements change.

Both CAN and SPI transmission are performed in the main function. When the FIFO is not empty, the FIFO element is fetched. The message is formatted and sent. For CAN, the CAN frame is a fixed format as shown in Table 2-1. For SPI, messages are sent in the format listed in SPI Packet Form.

Note that SPI is a communication method that sends and receives at the same time. When the master initiates sending a byte, the master expects to receive a byte. In the design of this document, SPI RX interrupt is not only used for the SPI to receive, but also used to fill the TX data into the SPI TX FIFO. If SPI functions in master mode, SPI communication starts immediately after SPI TX FIFO is stored by data. If the SPI works in slave mode, SPI uses IO to trigger the master to initiate communication after the data is stored. In this demo, users can select the SPI mode.

Figure 2-6 shows the FIFO structure. Each FIFO uses three global variables to indicate the FIFO status. For gSpi2Can_FIFO, gSpi2Can_FIFO.fifo_in indicates the write position, gSpi2Can_FIFO.fifo_out indicates the read position,and gSpi2Can_FIFO.fifo_Count indicates the number of elements in the gSpi2Can_FIFO.

If the gSpi2Can_FIFO is empty, gSpi2Can_FIFO.fifo_in equals gSpi2Can_FIFO.fifo_out, and gSpi2Can_FIFO.fifo_count is zero.

When performing processSpiRxMsg(), a new message from SPI is stored to gSpi2Can_FIFO. So the gSpi2Can_FIFO.fifo_in moves to the next position, and gSpi2Can_FIFO.fifo_count is incremented by 1.

When transmitting a message from gSpi2Can_FIFO to CAN, gSpi2Can_FIFO.fifo_out moves to the next position, and gSpi2Can_FIFO.fifo_count minus 1. gCan2Spi_FIFO is similar to gSpi2Can_FIFO.