SLAAEN5 February   2025 MSPM0G1106 , MSPM0G1107 , MSPM0G1506 , MSPM0G1507 , MSPM0G1518 , MSPM0G1519 , MSPM0G3106 , MSPM0G3106-Q1 , MSPM0G3107 , MSPM0G3107-Q1 , MSPM0G3506 , MSPM0G3506-Q1 , MSPM0G3507 , MSPM0G3507-Q1 , MSPM0G3518 , MSPM0G3518-Q1 , MSPM0G3519 , MSPM0G3519-Q1

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1Introduction
    1. 1.1 Bridge between CAN and SPI
  5. 2Implementation
    1. 2.1 Principle
    2. 2.2 Structure
  6. 3Software Description
    1. 3.1 Software Functionality
    2. 3.2 Configurable Parameters
    3. 3.3 Structure of Custom Element
    4. 3.4 Structure of FIFO
    5. 3.5 SPI Receive and Transmit (Transparent Transmission)
    6. 3.6 SPI Receive and Transmit (Protocol Transmission)
    7. 3.7 CAN Receive and Transmit
    8. 3.8 Application Integration
  7. 4Hardware
  8. 5Application Aspects
    1. 5.1 Flexible structure
    2. 5.2 Optional Configuration for SPI
    3. 5.3 Optional Configuration for CAN
    4. 5.4 CAN Bus Multinode Communication Example
  9. 6Summary
  10. 7References

Application Integration

Functions listed in Table 3-3 are categorized into different files. Functions for SPI receive and transmit are included in bridge_spi.c and bridge_spi.h. Functions for CAN receive and transmit are included in bridge_can.c and bridge_can.h. The structure of the FIFO element is defined in user_define.h.

Users can separate functions by file. For example, if only SPI functions are required, users can reserve bridge_spi.c and bridge_spi.h to call the functions.

For the basic configuration of peripherals, this project integrates a SysConfig configuration file. Users can easily modify the basic configuration of peripherals by using SysConfig.

Applications requiring this functionality must include the CAN module and API and SPI module API. All API files are included with the SDK download.

 Files Required by the
                    Software Figure 3-1 Files Required by the Software

Table 3-4 lists the footprint of the CAN-SPI bridge design in terms of flash size and RAM size. Table 3-4 have been determined using the Code Composer Studio (Version: 12.7.1.00001) with optimization level 2.

The user can adjust the size of the FIFO. A larger FIFO means more cache capacity, but requires more RAM space. For details, see the relevant content in Application Aspects. The user can configure the data field size according to the actual data length. As listed in Table 3-4, using a data field with less bytes can significantly reduce RAM usage.

Table 3-4 Memory Footprint of the CAN-SPI Bridge
Minimum Required Code Size (Bytes) Flash SRAM
CAN-SPI master bridge
(Protocol Transmission
S2C_FIFO_SIZE=8
C2S_FIFO_SIZE=8
Data size = 12 bytes)
6128 1466
CAN-SPI slave bridge
(Protocol Transmission
S2C_FIFO_SIZE=8
C2S_FIFO_SIZE=8
Data size = 12 bytes)
6344 1462
CAN-SPI master bridge
(Protocol Transmission
S2C_FIFO_SIZE=8

C2S_FIFO_SIZE=8
Data size = 64 bytes)
6224 2610
CAN-SPI slave bridge
(Protocol Transmission
S2C_FIFO_SIZE=8
C2S_FIFO_SIZE=8
Data size = 64 bytes)
6440 2606
CAN-SPI master bridge
(Protocol Transmission
S2C_FIFO_SIZE=30
C2S_FIFO_SIZE=30
Data size = 12 bytes)
6232 2522
CAN-SPI slave bridge
(Protocol Transmission
S2C_FIFO_SIZE=30
C2S_FIFO_SIZE=30
Data size = 12 bytes)
6448 2518