SLAAEU3 June 2025 MSPM0C1104
To start a PWM in a specific channel, the output can write a non-zero duty cycle into the specific duty cycle register (start from 0x20). To stop the PWM output, write zero duty cycle to the specific channel duty cycle register. The duty cycle valid bits for this demo is 9 bits and using two registers to identify one duty cycle in the channel. In this demo all the registers are one byte length.
This demo can also support to change the frequency of the PWM in the PWM frequency register (start from 0x10). Currently, the demo can support four different frequencies in the demo: 22.9Hz, 45.8Hz(default), 91.7Hz and 23.4kHz. The customer can change different frequencies as required in the code. Four bits can be used to configured different frequencies in one register, so one register can be used to configure two different timers. In the demo code, some PWM channels are generated in one timer. These PWMs can use the same frequency.