SLASEG6C May   2018  – September 2025 TAS3251

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Comparison Table
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Amplifier Electrical Characteristics
    6. 6.6  DAC Electrical Characteristics
    7. 6.7  Audio Characteristics (BTL)
    8. 6.8  Audio Characteristics (PBTL)
    9. 6.9  MCLK Timing
    10. 6.10 Serial Audio Port Timing – Target Mode
    11. 6.11 Serial Audio Port Timing – Controller Mode
    12. 6.12 I2C Bus Timing –Standard
    13. 6.13 I2C Bus Timing –Fast
    14. 6.14 Timing Diagrams
    15. 6.15 Typical Characteristics
      1. 6.15.1 BTL Configuration
      2. 6.15.2 PBTL Configuration
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Power-on-Reset (POR) Function
      2. 7.3.2  Enable Device
      3. 7.3.3  DAC and DSP Clocking
        1. 7.3.3.1 Internal Clock Error Notification (CLKE)
      4. 7.3.4  Serial Audio Port
        1. 7.3.4.1 Clock Controller Mode from Audio Rate Controller Clock
        2. 7.3.4.2 Clock Target Mode with 4-Wire Operation (SCLK, MCLK, LRCK/FS, SDIN)
        3. 7.3.4.3 Clock Target Mode with SCLK PLL to Generate Internal Clocks (3-Wire PCM)
          1. 7.3.4.3.1 Clock Generation Using the PLL
          2. 7.3.4.3.2 PLL Calculation
            1. 7.3.4.3.2.1 Examples:
        4. 7.3.4.4 Serial Audio Port – Data Formats and Bit Depths
          1. 7.3.4.4.1 Data Formats and Controller or Target Modes of Operation
        5. 7.3.4.5 Input Signal Sensing (Power-Save Mode)
      5. 7.3.5  Volume Control
        1. 7.3.5.1 DAC Digital Gain Control
          1. 7.3.5.1.1 Emergency Volume Ramp Down
      6. 7.3.6  SDOUT Port and Hardware Control Pin
      7. 7.3.7  I2C Communication Port
        1. 7.3.7.1 Target Address
        2. 7.3.7.2 Register Address Auto-Increment Mode
        3. 7.3.7.3 Packet Protocol
        4. 7.3.7.4 Write Register
        5. 7.3.7.5 Read Register
        6. 7.3.7.6 DSP Book, Page, and Register Update
          1. 7.3.7.6.1 Book and Page Change
          2. 7.3.7.6.2 Swap Flag
          3. 7.3.7.6.3 Example Use
      8. 7.3.8  Pop and Click Free Startup and Shutdown
      9. 7.3.9  Integrated Oscillator for Output Power Stage
        1. 7.3.9.1 Oscillator Synchronization and Target Mode
      10. 7.3.10 Device Output Stage Protection System
        1. 7.3.10.1 Error Reporting
        2. 7.3.10.2 Overload and Short Circuit Current Protection
        3. 7.3.10.3 Signal Clipping and Pulse Injector
        4. 7.3.10.4 DC Speaker Protection
        5. 7.3.10.5 Pin-to-Pin Short Circuit Protection (PPSC)
        6. 7.3.10.6 Overtemperature Protection OTW and OTE
        7. 7.3.10.7 Undervoltage Protection (UVP) and Power-on Reset (POR)
        8. 7.3.10.8 Fault Handling
        9. 7.3.10.9 Output Power Stage Reset
      11. 7.3.11 Initialization, Startup and Shutdown
        1. 7.3.11.1 Power Up and Startup Sequence
        2. 7.3.11.2 Power Down and Shutdown Sequence
        3. 7.3.11.3 Device Mute
        4. 7.3.11.4 Device Unmute
        5. 7.3.11.5 Device Reset
        6. 7.3.11.6 Mute with DAC_MUTE or Clock Error
          1. 7.3.11.6.1 Mute using DAC_MUTE
        7. 7.3.11.7 Mute using Serial Audio Port Clock
        8. 7.3.11.8 Muting before an Unplanned Shutdown with DAC_MUTE
        9. 7.3.11.9 Output Power Stage Startup Timing
    4. 7.4 Device Functional Modes
      1. 7.4.1 Serial Audio Port Operating Modes
        1. 7.4.1.1 Controller and Target Mode Clocking for Digital Serial Audio Port
      2. 7.4.2 Communication Port Operating Modes
      3. 7.4.3 Speaker Amplifier Operating Modes
        1. 7.4.3.1 Stereo Mode
        2. 7.4.3.2 Mono Mode
    5. 7.5 Programming
      1. 7.5.1 Audio Processing Features
      2. 7.5.2 Processing Block Description
        1. 7.5.2.1  Input Scale and Mixer
          1. 7.5.2.1.1 Example
        2. 7.5.2.2  Sample Rate Converter
        3. 7.5.2.3  Parametric Equalizers (PEQ)
        4. 7.5.2.4  BQ Gain Scale
        5. 7.5.2.5  Dynamic Parametric Equalizer (DPEQ)
        6. 7.5.2.6  Two-Band Dynamic Range Control
        7. 7.5.2.7  Automatic Gain Limiter
          1. 7.5.2.7.1 Softening Filter Alpha (AEA)
          2. 7.5.2.7.2 Softening Filter Omega (AEO)
          3. 7.5.2.7.3 Attack Rate
          4. 7.5.2.7.4 Release Rate
          5. 7.5.2.7.5 Attack Threshold
        8. 7.5.2.8  Fine Volume
        9. 7.5.2.9  THD Boost
        10. 7.5.2.10 Level Meter
      3. 7.5.3 Other Processing Block Features
        1. 7.5.3.1 Number Format
          1. 7.5.3.1.1 Coefficient Format Conversion
      4. 7.5.4 Checksum
        1. 7.5.4.1 Cyclic Redundancy Check (CRC) Checksum
        2. 7.5.4.2 Exclusive or (XOR) Checksum
    6. 7.6 Register Maps
      1. 7.6.1 Registers - Page 0
        1. 7.6.1.1  Register 1 (0x01)
        2. 7.6.1.2  Register 2 (0x02)
        3. 7.6.1.3  Register 3 (0x03)
        4. 7.6.1.4  Register 4 (0x04)
        5. 7.6.1.5  Register 6 (0x06)
        6. 7.6.1.6  Register 7 (0x07)
        7. 7.6.1.7  Register 8 (0x08)
        8. 7.6.1.8  Register 9 (0x09)
        9. 7.6.1.9  Register 12 (0x0C)
        10. 7.6.1.10 Register 13 (0x0D)
        11. 7.6.1.11 Register 14 (0x0E)
        12. 7.6.1.12 Register 15 (0x0F)
        13. 7.6.1.13 Register 16 (0x10)
        14. 7.6.1.14 Register 17 (0x11)
        15. 7.6.1.15 Register 18 (0x12)
        16. 7.6.1.16 Register 20 (0x14)
        17. 7.6.1.17 Register 21 (0x15)
        18. 7.6.1.18 Register 22 (0x16)
        19. 7.6.1.19 Register 23 (0x17)
        20. 7.6.1.20 Register 24 (0x18)
        21. 7.6.1.21 Register 27 (0x1B)
        22. 7.6.1.22 Register 28 (0x1C)
        23. 7.6.1.23 Register 29 (0x1D)
        24. 7.6.1.24 Register 30 (0x1E)
        25. 7.6.1.25 Register 32 (0x20)
        26. 7.6.1.26 Register 33 (0x21)
        27. 7.6.1.27 Register 34 (0x22)
        28. 7.6.1.28 Register 37 (0x25)
        29. 7.6.1.29 Register 40 (0x28)
        30. 7.6.1.30 Register 41 (0x29)
        31. 7.6.1.31 Register 42 (0x2A)
        32. 7.6.1.32 Register 43 (0x2B)
        33. 7.6.1.33 Register 44 (0x2C)
        34. 7.6.1.34 Register 59 (0x3B)
        35. 7.6.1.35 Register 60 (0x3C)
        36. 7.6.1.36 Register 61 (0x3D)
        37. 7.6.1.37 Register 62 (0x3E)
        38. 7.6.1.38 Register 63 (0x3F)
        39. 7.6.1.39 Register 64 (0x40)
        40. 7.6.1.40 Register 65 (0x41)
        41. 7.6.1.41 Register 67 (0x43)
        42. 7.6.1.42 Register 68 (0x44)
        43. 7.6.1.43 Register 69 (0x45)
        44. 7.6.1.44 Register 70 (0x46)
        45. 7.6.1.45 Register 71 (0x47)
        46. 7.6.1.46 Register 72 (0x48)
        47. 7.6.1.47 Register 73 (0x49)
        48. 7.6.1.48 Register 74 (0x4A)
        49. 7.6.1.49 Register 75 (0x4B)
        50. 7.6.1.50 Register 76 (0x4C)
        51. 7.6.1.51 Register 78 (0x4E)
        52. 7.6.1.52 Register 79 (0x4F)
        53. 7.6.1.53 Register 85 (0x55)
        54. 7.6.1.54 Register 86 (0x56)
        55. 7.6.1.55 Register 87 (0x57)
        56. 7.6.1.56 Register 88 (0x58)
        57. 7.6.1.57 Register 91 (0x5B)
        58. 7.6.1.58 Register 92 (0x5C)
        59. 7.6.1.59 Register 93 (0x5D)
        60. 7.6.1.60 Register 94 (0x5E)
        61. 7.6.1.61 Register 95 (0x5F)
        62. 7.6.1.62 Register 108 (0x6C)
        63. 7.6.1.63 Register 119 (0x77)
        64. 7.6.1.64 Register 120 (0x78)
      2. 7.6.2 Registers - Page 1
        1. 7.6.2.1 Register 1 (0x01)
        2. 7.6.2.2 Register 2 (0x02)
        3. 7.6.2.3 Register 6 (0x06)
        4. 7.6.2.4 Register 7 (0x07)
        5. 7.6.2.5 Register 9 (0x09)
  9. 8 Application and Implementation
    1. 8.1 Typical Applications
      1. 8.1.1 Stereo, Bridge Tied Load (BTL) Application
      2. 8.1.2 Mono, Parallel Bridge-Tied Load (PBTL) Application
        1. 8.1.2.1 Parallel Bridge-Tied Load (PBTL), Pre-Filter
        2. 8.1.2.2 Parallel Bridge-Tied Load, Post-Filter
      3. 8.1.3 Design Requirements
      4. 8.1.4 Detailed Design Procedure
        1. 8.1.4.1 Step One: Schematic and Layout Design
          1. 8.1.4.1.1 Decoupling Capacitor Recommendations
          2. 8.1.4.1.2 PVDD Capacitor Recommendations
          3. 8.1.4.1.3 BST Capacitors
          4. 8.1.4.1.4 Heatsink
        2. 8.1.4.2 Step Two: Configure the Fixed-Function Process Flow for Use with the Target System
        3. 8.1.4.3 Step Three: Software Integration
      5. 8.1.5 Two TAS3251 Device Configurations
        1. 8.1.5.1 2 x PBTL Application
        2. 8.1.5.2 2 x BTL + 1 x PBTL Application
      6. 8.1.6 Three or More TAS3251 Device Configurations
      7. 8.1.7 Application Curves
    2. 8.2 Power Supply Recommendations
      1. 8.2.1 Power Supplies
        1. 8.2.1.1 DAC_DVDD and DAC_AVDD Supplies
          1. 8.2.1.1.1 CPVSS, CN and CP Charge Pump
        2. 8.2.1.2 VDD Supply
        3. 8.2.1.3 GVDD_X Supply
        4. 8.2.1.4 PVDD Supply
        5. 8.2.1.5 BST Supply
    3. 8.3 Layout
      1. 8.3.1 Layout Guidelines
        1. 8.3.1.1 General Guidelines for TAS3251
        2. 8.3.1.2 Importance of PVDD Bypass Capacitor Placement
      2. 8.3.2 Layout Examples
        1. 8.3.2.1 Bridge-Tied Load (BTL) Layout Example
        2. 8.3.2.2 Parallel Bridge-Tied Load (PBTL), Pre-Filter
        3. 8.3.2.3 Parallel Bridge-Tied Load (PBTL), Post-Filter
  10. 9 Device and Documentation Support
    1. 9.1 Device Support
      1. 9.1.1 Device Nomenclature
      2. 9.1.2 Development Support
    2. 9.2 Receiving Notification of Documentation Updates
    3. 9.3 Support Resources
    4. 9.4 Trademarks
    5. 9.5 Electrostatic Discharge Caution
    6. 9.6 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

5 Pin Configuration and Functions

Figure 5-1 DKQ Package 56-Pin HSSOP with PowerPAD™, Top View
Table 5-1 Pin Functions
PIN TYPE(1) DESCRIPTION
NO. NAME
1 DAC_OUTB+ O Differential DAC output B+.
2 DAC_OUTB- O Differential DAC output B-.
3 DAC_OUTA- O Differential DAC output A-.
4 DAC_OUTA+ O Differential DAC output A+.
5 CPVSS P –3.3V negative charge pump supply output for DAC. Connect 1µF ceramic capacitor to GND. Refer to section: Power Supply Recommendations
6 CN P Negative pin for capacitor connection used in the line-driver charge pump. Connect 1µF ceramic capacitor from CN to CP. Refer to section: Power Supply Recommendations
7 GND G Ground pin for device.
8 CP P Positive pin for capacitor connection used in the line-driver charge pump. Connect 1µF capacitor from CN to CP. Refer to section: Power Supply Recommendations
9 DAC_DVDD P DAC power supply input for digital logic and charge pump. Connect 3.3V and a 1uF ceramic capacitor to GND. Refer to section: DAC_DVDD and DAC_AVDD Supplies
10 DGND G Ground reference for digital circuitry. Connect this pin to the system ground.
11 DVDD_REG P DAC voltage regulator output derived from DAC_DVDD supply for use for internal digital circuitry (1.8V). This pin is provided as a connection point for filtering capacitors for this supply and must not be used to power any external circuitry. Connect 1µF ceramic capacitor to GND. Refer to section: DAC_DVDD and DAC_AVDD Supplies
12 GVDD_A P Gate drive supply input for amplifier channel A. Connect 12V and a 0.1µF capacitor to GND. Refer to section: GVDD_X Supply
13 GND G Ground pin for device.
14 MODE I Output configuration mode selection. BTL = 0, PBTL = 1. Refer to table: Table 5-2
15 SPK_INA+ I Input signal for half-bridge A+.
16 SPK_INA- I Input signal for half-bridge A-.
17 OC_ADJ I / O Over-Current threshold programming pin. Refer to section: Overload and Short Circuit Current Protection
18 FREQ_ADJ I / O Oscillator frequency programming pin. Refer to section: Oscillator for Output Power Stage
19 OSC_IOM I / O PWM switching oscillator synchronization interface. Optional. Do not connect if unused. Refer to section: Oscillator Synchronization and Target Mode
20 OSC_IOP O PWM switching oscillator synchronization interface. Optional. Do not connect if unused. Refer to section: Oscillator Synchronization and Target Mode
21 DVDD P Internal voltage regulator, amplifier digital section. Connect 1 µF ceramic capacitor to GND. Refer to section: VDD Supply
22 GND G Ground pin for device.
23 AVDD P Internal voltage regulator, amplifier analog section. Connect 1µF ceramic capacitor to GND. Refer to section: VDD Supply
24 C_START O Startup ramp, requires a charging capacitor to GND. Connect 10nF to GND for best pop prevention. Refer to section: Section 7.3.8
25 SPK_INB+ I Input signal for half-bridge B+.
26 SPK_INB- I Input signal for half-bridge B-.
27 RESET_AMP I Device reset, active low. Use for amplifier reset and mute. Refer to section: Output Power Stage Reset
28 FAULT O Shutdown signal, open drain; active low. Internal pull-up resistor to DVDD. Do not connect if unused. Refer to section: Device Output Stage Protection System
29 CLIP_OTW O Clipping warning and over-temperature warning; open drain; active low. Internal pull-up resistor to DVDD. Do not connect if unused. Refer to section: Device Output Stage Protection System
30 GVDD_B P Gate drive supply input for amplifier channel B. Connect 12V and a 0.1µF capacitor to GND. Refer to section: GVDD_X Supply
31 BST_B- P HS bootstrap supply (BST), external 0.033μF capacitor to SPK_OUTB-. Refer to section: BST Supply
32 BST_B+ P HS bootstrap supply (BST), external 0.033μF capacitor to SPK_OUTB+. Refer to section: BST Supply
33 GND G Ground pin for device.
34 SPK_OUTB- O Output, half bridge B-.
35 PVDD_B P PVDD supply for channel B. Connect large bulk capacitor and 1µF ceramic decoupling capacitor to GND and place near pin. Refer to section: PVDD Supply
36 SPK_OUTB+ O Output, half bridge B+.
37 GND G Ground pin for device.
38 GND G Ground pin for device.
39 SPK_OUTA- O Output, half bridge A-.
40 PVDD_A P PVDD supply for channel A. Connect large bulk capacitor and 1 µF ceramic decoupling capacitor to GND and place near pin. Refer to section: PVDD Supply
41 SPK_OUTA+ O Output, half bridge A+.
42 GND G Ground pin for device.
43 BST_A- P HS bootstrap supply (BST), external 0.033μF capacitor to SPK_OUTA-. Refer to section: BST Supply
44 BST_A+ P HS bootstrap supply (BST), external 0.033μF capacitor to SPK_OUTA+. Refer to section: BST Supply
45 DAC_MUTE I Hardware controlled DAC mute function. Pull low (connected to DGND) to mute the device and pull high (connected to DAC_DVDD) to unmute the device. Refer to section: Section 7.3.11.6
46 ADR I Sets the LSB of the I2C address to 0 if pulled to GND, to 1 if pulled to DAC_DVDD. Refer to table: I2C Device Target Address
47 LRCK I Left-Right Word (I2S) or Frame (TDM) select clock for digital audio signal. In I2S, LJ, and RJ, this corresponds to the left channel and right channel boundary. In TDM mode, this corresponds to the frame sync boundary. Refer to section: Serial Audio Port
48 SDIN I Audio data serial port, data in. Refer to section: Serial Audio Port
49 SCLK I Serial or bit clock for the digital signal that is active on the input data line of the serial data port. Refer to section: Serial Audio Port
50 MCLK I Controller clock used for internal clock tree and sub-circuit and state machine clocking. Refer to section: Serial Audio Port
51 SDOUT I / O Audio data serial port, data output. Refer to section: SDOUT Port and Hardware Control Pin
52 XPU I External pull-up, logic level pin. For normal operation, this pin should be connected directly to 3.3V (DAC_DVDD or DAC_AVDD).
53 SCL I I2C serial control port clock. Refer to section: I2C Communication Port
54 SDA I / O I2C serial control port data. Refer to section: I2C Communication Port
55 AGND G Ground reference for analog circuitry. Connect to system ground.
56 DAC_AVDD P DAC power supply input for DAC internal analog circuitry. Connect 3.3V and a 1uF ceramic capacitor to GND. Refer to section: DAC_DVDD and DAC_AVDD Supplies
PowerPAD G Ground, connect to grounded heat sink.
(1) I = Input, O = Output, I/O = Input/Output, P = Power, G = Ground
Table 5-2 Mode Selection Pins
Output Configuration Input Mode MODE Pin SPK_INB+ Pin SPK_INB- Pin Description
2 x BTL 2N + 1 0 X X Stereo BTL output configuration
1 x PBTL 2N + 1 1 0 0 Paralleled BTL configuration pre-filter or post-filter. Connect SPK_INB+ and INPUT_B- to GND with no DC blocking capacitor.
Table 5-3 I2C Device Target Address
ADR Pin Hex Binary
0 7-bit Address 0x4A 1001 010
7-bit Address + Write Bit 0x94 1001 0100
7-bit Address + Read Bit 0x95 1001 0101
1 7-bit Address 0x4B 1001 011
7-bit Address + Write Bit 0x96 1001 0110
7-bit Address + Read Bit 0x97 1001 0111