SLASEU7A March   2023  – October 2026 AFE781H1 , AFE881H1

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings
    3. 5.3  Recommended Operating Conditions
    4. 5.4  Thermal Information
    5. 5.5  Electrical Characteristics
    6. 5.6  Timing Requirements
    7. 5.7  Timing Diagrams
    8. 5.8  Typical Characteristics: VOUT DAC
    9. 5.9  Typical Characteristics: ADC
    10. 5.10 Typical Characteristics: Reference
    11. 5.11 Typical Characteristics: HART Modem
    12. 5.12 Typical Characteristics: Power Supply
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 Digital-to-Analog Converter (DAC) Overview
        1. 6.3.1.1 DAC Resistor String
        2. 6.3.1.2 DAC Buffer Amplifier
        3. 6.3.1.3 DAC Transfer Function
        4. 6.3.1.4 DAC Gain and Offset Calibration
        5. 6.3.1.5 Programmable Slew Rate
        6. 6.3.1.6 DAC Register Structure and CLEAR State
      2. 6.3.2 Analog-to-Digital Converter (ADC) Overview
        1. 6.3.2.1 ADC Operation
        2. 6.3.2.2 ADC Custom Channel Sequencer
        3. 6.3.2.3 ADC Synchronization
        4. 6.3.2.4 ADC Offset Calibration
        5. 6.3.2.5 External Monitoring Inputs
        6. 6.3.2.6 Temperature Sensor
        7. 6.3.2.7 Self-Diagnostic Multiplexer
        8. 6.3.2.8 ADC Bypass
      3. 6.3.3 Programmable Out-of-Range Alarms
        1. 6.3.3.1 Alarm-Based Interrupts
        2. 6.3.3.2 Alarm Action Configuration Register
        3. 6.3.3.3 Alarm Voltage Generator
        4. 6.3.3.4 Temperature Sensor Alarm Function
        5. 6.3.3.5 Internal Reference Alarm Function
        6. 6.3.3.6 ADC Alarm Function
        7. 6.3.3.7 Fault Detection
      4. 6.3.4 IRQ
      5. 6.3.5 HART Interface
        1. 6.3.5.1  FIFO Buffers
          1. 6.3.5.1.1 FIFO Buffer Access
          2. 6.3.5.1.2 FIFO Buffer Flags
        2. 6.3.5.2  HART Modulator
        3. 6.3.5.3  HART Demodulator
        4. 6.3.5.4  HART Modem Modes
          1. 6.3.5.4.1 Half-Duplex Mode
          2. 6.3.5.4.2 Full-Duplex Mode
        5. 6.3.5.5  HART Modulation and Demodulation Arbitration
          1. 6.3.5.5.1 HART Receive Mode
          2. 6.3.5.5.2 HART Transmit Mode
        6. 6.3.5.6  HART Modulator Timing and Preamble Requirements
        7. 6.3.5.7  HART Demodulator Timing and Preamble Requirements
        8. 6.3.5.8  IRQ Configuration for HART Communication
        9. 6.3.5.9  HART Communication Using the SPI
        10. 6.3.5.10 HART Communication Using UART
        11. 6.3.5.11 Memory Built-In Self-Test (MBIST)
      6. 6.3.6 Internal Reference
      7. 6.3.7 Integrated Precision Oscillator
      8. 6.3.8 One-Time Programmable (OTP) Memory
    4. 6.4 Device Functional Modes
      1. 6.4.1 DAC Power-Down Mode
      2. 6.4.2 Reset
    5. 6.5 Programming
      1. 6.5.1 Communication Setup
        1. 6.5.1.1 SPI Mode
        2. 6.5.1.2 UART Mode
        3. 6.5.1.3 SPI Plus UART Mode
        4. 6.5.1.4 HART Functionality Setup Options
      2. 6.5.2 Serial Peripheral Interface (SPI)
        1. 6.5.2.1 SPI Frame Definition
        2. 6.5.2.2 SPI Read and Write
        3. 6.5.2.3 Frame Error Checking
        4. 6.5.2.4 Synchronization
      3. 6.5.3 UART Interface
        1. 6.5.3.1 UART Break Mode (UBM)
          1. 6.5.3.1.1 Interface With FIFO Buffers and Register Map
      4. 6.5.4 Status Bits
      5. 6.5.5 Watchdog Timer
    6. 6.6 Register Maps
      1. 6.6.1 AFEx81H1 Registers
  8. 7 Application and Implementation
    1. 7.1 Application Information
      1. 7.1.1 Multichannel Configuration
    2. 7.2 Typical Application
      1. 7.2.1 4mA to 20mA Current Transmitter
        1. 7.2.1.1 Design Requirements
        2. 7.2.1.2 Detailed Design Procedure
          1. 7.2.1.2.1 Start-Up Circuit
          2. 7.2.1.2.2 Current Loop Control
          3. 7.2.1.2.3 Input Protection and Rectification
          4. 7.2.1.2.4 System Current Budget
        3. 7.2.1.3 Application Curves
    3. 7.3 Initialization Set Up
    4. 7.4 Power Supply Recommendations
    5. 7.5 Layout
      1. 7.5.1 Layout Guidelines
      2. 7.5.2 Layout Example
  9. 8 Device and Documentation Support
    1. 8.1 Documentation Support
      1. 8.1.1 Related Documentation
    2. 8.2 Receiving Notification of Documentation Updates
    3. 8.3 Support Resources
    4. 8.4 Trademarks
    5. 8.5 Electrostatic Discharge Caution
    6. 8.6 Glossary
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information

6.3.1.3 DAC Transfer Function

The following equation describes the DAC transfer function, which is the relationship between internal signal DAC_CODE and output voltage VOUT:

Equation 1. V O U T = D A C _ C O D E 2 N × F S R + V M I N

where

  • DAC_CODE is an internal signal and the decimal equivalent of the gain and offset calibrated binary code loaded into the DAC_DATA register. DAC_CODE range = 0 to 2N – 1.
  • N = DAC_CODE resolution in bits (16 for the AFE881H1 and 14 for the AFE781H1).
  • FSR = VOUT full-scale range for the selected output range in Table 6-2.
  • VMIN = the lowest voltage for the selected DAC output range.
Table 6-2 FSR and VMIN for all VOUT Ranges
PVDD DAC_CFG.RANGE VOUT RANGE FSR VMIN
1.8V 0 0.15V to 1.25V 1.1V 0.15V
1.8V 1 0.2V to 1.0V 0.8V 0.2V
≥ 2.7V 0 0.3V to 2.5V 2.2V 0.3V
≥ 2.7V 1 0.4V to 2.0V 1.6V 0.4V

The VOUT range for the DAC is determined by DAC_CFG.RANGE bit when not in the CLEAR state. In the CLEAR state, the range is determined by DAC_CFG.CLR_RANGE bit.