SLASEU7A March   2023  – October 2026 AFE781H1 , AFE881H1

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings
    3. 5.3  Recommended Operating Conditions
    4. 5.4  Thermal Information
    5. 5.5  Electrical Characteristics
    6. 5.6  Timing Requirements
    7. 5.7  Timing Diagrams
    8. 5.8  Typical Characteristics: VOUT DAC
    9. 5.9  Typical Characteristics: ADC
    10. 5.10 Typical Characteristics: Reference
    11. 5.11 Typical Characteristics: HART Modem
    12. 5.12 Typical Characteristics: Power Supply
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 Digital-to-Analog Converter (DAC) Overview
        1. 6.3.1.1 DAC Resistor String
        2. 6.3.1.2 DAC Buffer Amplifier
        3. 6.3.1.3 DAC Transfer Function
        4. 6.3.1.4 DAC Gain and Offset Calibration
        5. 6.3.1.5 Programmable Slew Rate
        6. 6.3.1.6 DAC Register Structure and CLEAR State
      2. 6.3.2 Analog-to-Digital Converter (ADC) Overview
        1. 6.3.2.1 ADC Operation
        2. 6.3.2.2 ADC Custom Channel Sequencer
        3. 6.3.2.3 ADC Synchronization
        4. 6.3.2.4 ADC Offset Calibration
        5. 6.3.2.5 External Monitoring Inputs
        6. 6.3.2.6 Temperature Sensor
        7. 6.3.2.7 Self-Diagnostic Multiplexer
        8. 6.3.2.8 ADC Bypass
      3. 6.3.3 Programmable Out-of-Range Alarms
        1. 6.3.3.1 Alarm-Based Interrupts
        2. 6.3.3.2 Alarm Action Configuration Register
        3. 6.3.3.3 Alarm Voltage Generator
        4. 6.3.3.4 Temperature Sensor Alarm Function
        5. 6.3.3.5 Internal Reference Alarm Function
        6. 6.3.3.6 ADC Alarm Function
        7. 6.3.3.7 Fault Detection
      4. 6.3.4 IRQ
      5. 6.3.5 HART Interface
        1. 6.3.5.1  FIFO Buffers
          1. 6.3.5.1.1 FIFO Buffer Access
          2. 6.3.5.1.2 FIFO Buffer Flags
        2. 6.3.5.2  HART Modulator
        3. 6.3.5.3  HART Demodulator
        4. 6.3.5.4  HART Modem Modes
          1. 6.3.5.4.1 Half-Duplex Mode
          2. 6.3.5.4.2 Full-Duplex Mode
        5. 6.3.5.5  HART Modulation and Demodulation Arbitration
          1. 6.3.5.5.1 HART Receive Mode
          2. 6.3.5.5.2 HART Transmit Mode
        6. 6.3.5.6  HART Modulator Timing and Preamble Requirements
        7. 6.3.5.7  HART Demodulator Timing and Preamble Requirements
        8. 6.3.5.8  IRQ Configuration for HART Communication
        9. 6.3.5.9  HART Communication Using the SPI
        10. 6.3.5.10 HART Communication Using UART
        11. 6.3.5.11 Memory Built-In Self-Test (MBIST)
      6. 6.3.6 Internal Reference
      7. 6.3.7 Integrated Precision Oscillator
      8. 6.3.8 One-Time Programmable (OTP) Memory
    4. 6.4 Device Functional Modes
      1. 6.4.1 DAC Power-Down Mode
      2. 6.4.2 Reset
    5. 6.5 Programming
      1. 6.5.1 Communication Setup
        1. 6.5.1.1 SPI Mode
        2. 6.5.1.2 UART Mode
        3. 6.5.1.3 SPI Plus UART Mode
        4. 6.5.1.4 HART Functionality Setup Options
      2. 6.5.2 Serial Peripheral Interface (SPI)
        1. 6.5.2.1 SPI Frame Definition
        2. 6.5.2.2 SPI Read and Write
        3. 6.5.2.3 Frame Error Checking
        4. 6.5.2.4 Synchronization
      3. 6.5.3 UART Interface
        1. 6.5.3.1 UART Break Mode (UBM)
          1. 6.5.3.1.1 Interface With FIFO Buffers and Register Map
      4. 6.5.4 Status Bits
      5. 6.5.5 Watchdog Timer
    6. 6.6 Register Maps
      1. 6.6.1 AFEx81H1 Registers
  8. 7 Application and Implementation
    1. 7.1 Application Information
      1. 7.1.1 Multichannel Configuration
    2. 7.2 Typical Application
      1. 7.2.1 4mA to 20mA Current Transmitter
        1. 7.2.1.1 Design Requirements
        2. 7.2.1.2 Detailed Design Procedure
          1. 7.2.1.2.1 Start-Up Circuit
          2. 7.2.1.2.2 Current Loop Control
          3. 7.2.1.2.3 Input Protection and Rectification
          4. 7.2.1.2.4 System Current Budget
        3. 7.2.1.3 Application Curves
    3. 7.3 Initialization Set Up
    4. 7.4 Power Supply Recommendations
    5. 7.5 Layout
      1. 7.5.1 Layout Guidelines
      2. 7.5.2 Layout Example
  9. 8 Device and Documentation Support
    1. 8.1 Documentation Support
      1. 8.1.1 Related Documentation
    2. 8.2 Receiving Notification of Documentation Updates
    3. 8.3 Support Resources
    4. 8.4 Trademarks
    5. 8.5 Electrostatic Discharge Caution
    6. 8.6 Glossary
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information

5.5 Electrical Characteristics

all minimum and maximum values at TA = –40°C to +125°C and all typical values at TA = 25°C, PVDD = VDD = IOVDD = 1.8V, external or internal VREFIO = 1.25V, RLOAD = 50kΩ to GND, CLOAD = 100pF to GND, and digital inputs at IOVDD or GND (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VOUT DAC STATIC PERFORMANCE
Resolution AFE881H1 16 Bits
AFE781H1 14
INL Integral nonlinearity(1) AFE881H1 –4 4 LSB
AFE781H1 –2 2
DNL Differential nonlinearity(1) –1 1 LSB
TUE Total unadjusted error(1) TA = –40°C to +125°C –0.07 0.07 %FSR
TA = –40°C to +85°C –0.05 0.05
TA = 25°C –0.04 0.04
ZCE Zero code error TA = –40°C to +125°C –0.07 0.07 %FSR
TA = –40°C to +85°C –0.05 0.05
TA = 25°C –0.03 0.03
ZCE-TC Zero code error temperature coefficient ±3 ppm/°C
OE Offset error(1) TA = –40°C to +125°C –0.07 0.07 %FSR
TA = –40°C to +85°C –0.05 0.05
TA = 25°C –0.03 0.03
OE-TC Offset error temperature coefficient (1) ±3 ppm/°C
GE Gain error(1) TA = –40°C to +125°C –0.04 0.04 %FSR
TA = –40°C to +85°C –0.04 0.04
TA = 25°C –0.03 0.03
GE-TC Gain error temperature coefficient(1) ±3 ppm FSR/°C
FSE Full-scale error TA = –40°C to +125°C –0.07 0.07 %FSR
TA = –40°C to +85°C –0.06 0.06
TA = 25°C –0.04 0.04
FSE-TC Full-scale error temperature coefficient ±3 ppm FSR/°C
VOUT DAC DYNAMIC PERFORMANCE
ts Output voltage settling time(4) ¼ to ¾ scale and ¾ to ¼ scale settling to ±2LSB,
PVDD = VDD = 1.8V, VREFIO = 1.25V		 65 µs
10mV step settling to ±2LSB,
PVDD = VDD = 1.8V, VREFIO = 1.25V		 30
SR Slew rate(4) Fullscale transition measured from 10% to 90% 30 mV/µs
Vn Output noise(4) 0.1Hz to 10Hz, DAC at midscale,
PVDD = VDD = 1.8V, VREFIO = 1.25V		 0.25 LSBPP
100kHz bandwidth, DAC at midscale,
PVDD = VDD = 1.8V, VREFIO = 1.25V		 32 µVrms
Vn Output noise density Measured at 1kHz, DAC at midscale,
PVDD = VDD = 1.8V, VREFIO = 1.25V		 180 nV/√Hz
Measured at 1kHz, DAC at midscale,
PVDD = 5V, VREFIO = 1.25V		 260
Power supply rejection ratio (AC) 200mV 50Hz to 60Hz sine wave superimposed on power supply voltage, DAC at midscale. 85 dB
Code change glitch impulse Midcode ±1LSB (including feedthrough)
PVDD = VDD = 1.8V, VREFIO = 1.25V		 4.5 nV-s
Code change glitch magnitude Midcode ±1LSB (including feedthrough)
PVDD = 5V, VREFIO = 1.25V		 1.5 mV
Digital feedthrough At SCLK = 1MHz, DAC output at midscale 1 nV-s
VOUT DAC OUTPUT CHARACTERISTICS
Output voltage range RANGE = 0, PVDD = VDD 0.15 1.25 V
RANGE = 1, PVDD = VDD 0.2 1.0
RANGE = 0, PVDD > 2.7V, VDD generated 0.3 2.5
RANGE = 1, PVDD > 2.7V, VDD generated 0.4 2.0
VOUT alarm output high PVDD > 2.7V, VDD internally generated –6% 2.5 +6% V
PVDD = VDD –6% 1.25 +6%
VOUT alarm output low PVDD > 2.7V, VDD internally generated –5% 0.3 +5% V
PVDD = VDD –5% 0.15 +5%
RLOAD Resistive load(2) 10 kΩ
CLOAD Capacitive load(2) 100 pF
Load regulation DAC at midscale, –1mA ≤ IOUT ≤ +1mA 10 µV/mA
Short-circuit current Full scale output shorted to GND 5 mA
Zero output shorted to VDD 5
Output voltage headroom to PVDD DAC at full code, IOUT = 1mA (sourcing) 200 mV
Output voltage footroom to GND DAC at zero code, IOUT = 1mA (sinking) 200 mV
ZO DC small signal output impedance DAC at midscale 10 mΩ
Output Hi-Z 500 kΩ
Power supply rejection ratio (dc) DAC at midscale; PVDD = 1.8V ± 10% 0.1 mV/V
Output voltage drift vs time, 1000 hours TA = 35°C, VOUT = midscale, ideal VREF ±5 ppm FSR
DIAGNOSTIC ADC
Input voltage range PVDD = VDD 0 1.25 V
PVDD > 2.7V 0 2.5
Resolution 12 Bits
DNL Differential nonlinearity Specified 12-bit monotonic –1 ±0.2 1 LSB
INL Integral nonlinearity –4 ±1 4 LSB
OE Offset error After calibration –10 ±1.6 10 LSB
GE Gain error –0.8 ±0.13 0.8 %FSR
Noise ±4 LSB
Input capacitance 6 pF
Input bias current ADC not converting –50 50 nA
Acquisition time 52 µs
Conversion time 210 µs
Conversion rate 3.84 kSPS
Temperature sensor accuracy 5 °C
INTERNAL OSCILLATOR
Frequency TA = –40°C to +125°C 1.2165 1.2288 1.2411 MHz
HART MODEM
RX_IN INPUT (HART MODE)
Input voltage range External or internal reference source, design architecture. Signal applied at the input to the dc blocking capacitor. 0 1.5 VPP
Receiver sensitivity Threshold for successful carrier detection and demodulation, assuming ideal sinusoidal input FSK signals with valid preamble using internal filter. 80 100 120 mVPP
Carrier detect time 1200Hz of carrier frequency present at the input before CD asserted 3 baud
MOD_OUT OUTPUT (HART MODE)
Output voltage Measured at MOD_OUT pin with 160Ω load,
AC-coupled (2.2 µF)		 400 500 800 mVPP
Mark frequency 1200 Hz
Space frequency 2200 Hz
Frequency error TA = –40°C to +125°C –1 1 %
Phase continuity error Design architecture 0 Degrees
Minimum resistive load AC-coupled with 2.2 µF 160 Ω
Transmit impedance RTS low, measured at the MOD_OUT pin,
1mA measurement current		 25 mΩ
Transmit impedance RTS high, measured at the MOD_OUT pin,
±200nA measurement current		 50 kΩ
VOLTAGE REFERENCE INPUT
ZVREFIO Reference input impedance (VREFIO) RANGE = 0 125 kΩ
RANGE = 1 180
CVREFIO Reference input capacitance (VREFIO) 100 pF
VOLTAGE REFERENCE OUTPUT
Output (initial accuracy)(3) TA = 25°C 1.248 1.25 1.252 V
Output drift(3) TA = –40°C to +125°C 10 ppm/℃
Output impedance(3) 0.1 Ω
Output noise(3) 0.1Hz to 10Hz 7.5 µVPP
Output noise density(3) Measured at 10kHz, reference load = 100nF 200 nV/√Hz
Load current(3) Sourcing, 0.1% VREF change from nominal 2.5 mA
Sinking, 0.1% VREF change from nominal 0.3
Load regulation(3) Sourcing, 0mA to 2.5mA 4 µV/mA
COUT Stable output capacitance TA = –40°C to +125°C, 
ESR from 10mΩ to 400mΩ		 70 100 130 nF
Line regulation(3) 80 µV/V
Output voltage drift vs time(3) TA = 35°C, 1000 hours ±100 ppm
Thermal hysteresis(3) 1st cycle 500 µV
Additional cycles 25 µV
VDD VOLTAGE REGULATOR OUTPUT
Output voltage 1.71 1.8 1.89 V
Output impedance(3) PVDD = 3.3V, sourcing, 0.5mA to 2.5mA 3 Ω
Load current(3) PVDD = 3.3V, sourcing, 1% VDD change from nominal 4 mA
THERMAL ALARM
Alarm trip point 130 °C
Warning trip point 85 °C
Hysteresis 12 °C
Trip point absolute accuracy 5 °C
Trip point relative accuracy 2 °C
DIGITAL INPUT CHARACTERISTICS
VIH High-level input voltage 0.7 V/IOVDD
VIL Low-level input voltage 0.3 V/IOVDD
Hysteresis voltage 0.05 V/IOVDD
Input current –400 400 nA
Pin capacitance Per pin 10 pF
DIGITAL OUTPUT CHARACTERISTICS
VOH High-level output voltage ISOURCE = 1mA 0.8 V/IOVDD
VOL Low-level output voltage ISINK = 1mA 0.2 V/IOVDD
VOL Open-drain low-level output voltage ISINK = 2mA 0.3 V
Output pin capacitance 10 pF
POWER REQUIREMENTS
IPVDD Current flowing into PVDD PVDD only, VDD internally generated, DAC at zero-scale, ADC and SPI static 180 220 µA
Shared PVDD and VDD connection, DAC at zero-scale, ADC and SPI static 32 45
ILDO VDD LDO quiescent current From PVDD 8 µA
IVDD Current flowing into VDD Shared PVDD and VDD connection, DAC at zero-scale, ADC and SPI static, internal reference 140 170 µA
IREFIO Internal reference current consumption From external or internally generated VDD 52 70 µA
IHART HART Tx modem current consumption From external or internally generated VDD 10 µA
IADC ADC current consumption From PVDD, ADC converting at 3.84 kSPS 10 µA
CVDD Recommended VDD decoupling capacitance 1 10 µF
IIOVDD Current flowing into IOVDD SPI static 5 20 µA
IVREFIO Current flowing into VREFIO 0.15V to 1.25V range, midscale code 10 µA
(1) End point fit between code 0 to code 65,535 for 16-bit, code 0 to code 16,383 for 14-bit, DAC output unloaded, performance under resistive and capacitive load conditions are specified by design and characterization.
(2) Not production tested.
(3) Derived from the characterization data.
(4) Output buffer gain (G) = 2, PVDD > 2.7V.