SLASFJ7 July   2024 MSPM0C1106-Q1

ADVANCE INFORMATION  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Functional Block Diagram
  6. 5 Device Comparison
  7. 6 Pin Configuration and Functions
    1. 6.1 Pin Diagrams
    2. 6.2 Pin Attributes
      1.      10
    3. 6.3 Signal Descriptions
      1.      12
      2.      13
      3.      14
      4.      15
      5.      16
      6.      17
      7.      18
      8.      19
      9.      20
      10.      21
      11.      22
      12.      23
    4. 6.4 Connections for Unused Pins
  8. 7 Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Recommended Operating Conditions
    4. 7.4  Thermal Information
    5. 7.5  Supply Current Characteristics
      1. 7.5.1 RUN/SLEEP Modes
      2. 7.5.2 STOP/STANDBY Modes
      3. 7.5.3 SHUTDOWN Mode
    6. 7.6  Power Supply Sequencing
      1. 7.6.1 Power Supply Ramp
      2. 7.6.2 POR and BOR
    7. 7.7  Flash Memory Characteristics
    8. 7.8  Timing Characteristics
    9. 7.9  Clock Specifications
      1. 7.9.1 System Oscillator (SYSOSC)
      2. 7.9.2 Low Frequency Oscillator (LFOSC)
      3. 7.9.3 High Frequency Crystal/Clock
      4. 7.9.4 Low Frequency Crystal/Clock
    10. 7.10 Digital IO
      1. 7.10.1 Electrical Characteristics
      2. 7.10.2 Switching Characteristics
    11. 7.11 Analog Mux VBOOST
    12. 7.12 ADC
      1. 7.12.1 Electrical Characteristics
      2. 7.12.2 Switching Characteristics
      3. 7.12.3 Linearity Parameters
      4. 7.12.4 Typical Connection Diagram
    13. 7.13 Temperature Sensor
    14. 7.14 VREF
      1. 7.14.1 Electrical Characteristics
      2. 7.14.2 Voltage Characteristics
    15. 7.15 Comparator (COMP)
      1. 7.15.1 Comparator Electrical Characteristics
    16. 7.16 I2C
      1. 7.16.1 I2C Characteristics
      2. 7.16.2 I2C Filter
      3. 7.16.3 I2C Timing Diagram
    17. 7.17 SPI
      1. 7.17.1 SPI
      2. 7.17.2 SPI Timing Diagram
    18. 7.18 UART
    19. 7.19 TIMx
    20. 7.20 Emulation and Debug
      1. 7.20.1 SWD Timing
  9. 8 Detailed Description
    1. 8.1  Overview
    2. 8.2  CPU
    3. 8.3  Operating Modes
      1. 8.3.1 Functionality by Operating Mode
    4. 8.4  Power Management Unit (PMU)
    5. 8.5  Clock Module (CKM)
    6. 8.6  DMA_B
    7. 8.7  Events
    8. 8.8  Memory
      1. 8.8.1 Memory Organization
      2. 8.8.2 Peripheral File Map
      3. 8.8.3 Peripheral Interrupt Vector
    9. 8.9  Flash Memory
    10. 8.10 SRAM
    11. 8.11 GPIO
    12. 8.12 IOMUX
    13. 8.13 ADC
    14. 8.14 Temperature Sensor
    15. 8.15 Low-Frequency Sub System (LFSS)
    16. 8.16 VREF
    17. 8.17 COMP
    18. 8.18 Security
    19. 8.19 CRC
    20. 8.20 UART
    21. 8.21 I2C
    22. 8.22 SPI
    23. 8.23 IWDT
    24. 8.24 WWDT
    25. 8.25 RTC_B
    26. 8.26 Timers (TIMx)
    27. 8.27 Device Analog Connections
    28. 8.28 Input/Output Diagrams
    29. 8.29 Serial Wire Debug Interface
    30. 8.30 Device Factory Constants
    31. 8.31 Identification
  10. 9 Applications, Implementation, and Layout
    1. 9.1 Typical Application
      1. 9.1.1 Schematic
  11. 10Device and Documentation Support
    1. 10.1 Getting Started and Next Steps
    2. 10.2 Device Nomenclature
    3. 10.3 Tools and Software
    4. 10.4 Documentation Support
    5. 10.5 Support Resources
    6. 10.6 Trademarks
    7. 10.7 Electrostatic Discharge Caution
    8. 10.8 Glossary
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information

7.12.1 Electrical Characteristics

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted), all TYP values are measured at 25℃ and all accuracy parameters are measured using 12-bit resolution mode (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Vin(ADC) Analog input voltage range(1) Applies to all ADC analog input pins 0 VDD V
VR+ Positive ADC reference voltage VR+ sourced from VDD VDD V
VR+ sourced from external reference pin (VREF+) 1.4 VDD V
VR+ sourced from internal reference (VREF) VREF V
VR- Negative ADC reference voltage 0 V
FS ADC sampling frequency RES = 0x0 (12-bit mode), External Reference 1.6 Msps
I(ADC) Operating supply current
into VDD terminal		 FS = 1.6MSPS, External reference, VR+ = VDD 350 μA
FS = 500ksps, Internal reference, VR+ = VREF = 2.5V 300
CS/H ADC sample-and-hold capacitance 0.22 pF
Rin ADC sampling switch resistance 15 kΩ
ENOB Effective number of bits Internal reference, VR+ = VREF = 2.5V, Fin = 10KHz 9.4 10.2 bit
External reference, Fin = 10KHz (2) 10 10.8
SNR Signal-to-noise ratio External reference (2) 68 dB
Internal reference, VR+ = VREF = 2.5V 64
PSRRDC Power supply rejection ratio, DC External reference (2), VDD = VDD(min) to VDD(max) 68 dB
VDD = VDD(min) to VDD(max)
Internal reference, VR+ = VREF = 2.5V		 61
PSRRAC Power supply rejection ratio, AC External reference (2), ΔVDD = 0.1 V at 1 kHz 61 dB
ΔVDD = 0.1 V at 1 kHz
Internal reference, VR+ = VREF = 2.5V		 49
Twakeup ADC Wakeup Time Assumes internal reference is active 5 us
VSupplyMon Supply Monitor voltage divider (VDD/3) accuracy ADC input channel: Supply Monitor(3) -1.5 +1.5 %
ISupplyMon Supply Monitor voltage divider current consumption ADC input channel: Supply Monitor 10 uA
(1) The analog input voltage range must be within the selected ADC reference voltage range VR+ to VR– for valid conversion results.
(2) All external reference specifications are measured with VR+ = VREF+ = VDD = 3.3V and VR- = VREF- = VSS = 0V and external 1uF cap on VREF+ pin
(3) Analog power supply monitor. Analog input on channel 15 is disconnected and is internally connected to the voltage divider which is VDD/3.