SLCA006 June   2025 LM339 , LM393 , LMH7322 , TL331 , TLV1812 , TLV1871 , TLV1872 , TLV3601 , TLV3604

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1Introduction
  5. 2Output Types
    1. 2.1 Open Collector or Open Drain
      1. 2.1.1 Selectable Open Collector or Open Emitter Output
    2. 2.2 Push-Pull
      1. 2.2.1 Push-Pull with Separate Supplies
    3. 2.3 Differential
      1. 2.3.1 Differential Push Pull
      2. 2.3.2 ECL, RSECL, PECL, RSPECL, and LVPECL
      3. 2.3.3 Low Voltage Differential Signaling
      4. 2.3.4 Current Mode Logic
  6. 3Summary
  7. 4References

Low Voltage Differential Signaling

The Low Voltage Differential Signaling (LVDS) output stage uses a switched ±4mA current between the outputs and eliminates the negative supplies and the two pull-down resistors as required for ECL based outputs. LVDS further reduces the output swing to ±400mV centered on +1.2V.

 LVDS Output Figure 2-12 LVDS Output

The LVDS termination is easy to implement with just a single 100Ω termination resistor between the outputs at the receiver. The 100Ω resistor combined with the ±4mA differential current creates the ±400mV differential signal at the receiver.

 LVDS Termination Figure 2-13 LVDS Termination

LVDS, also known as TIA/EIA-644, is also the basis of many popular interlink protocols, such as Display Port, FPD-Link, Channel Link, Firewire, and Serial ATA. Many processors and ASIC's have native LVDS inputs with internal termination resistors.

Examples of devices that support the LVDS standard are the LMH7220, TLV3604/5/7, TLV3801/2 and TLV3811/11C.

Table 2-7 Advantages and Disadvantages of LVDS Outputs
Advantages Disadvantages
  • Even lower output swing increases speed
  • Single supply operation down to +1.8V
  • Lower power (50-100mW)
  • Single 100Ω termination resistor
  • Directly interfaces with matched impedance lines
  • High common mode rejection
  • Balanced lines reduce radiated EMI
  • Common standard on ASIC and processor inputs
  • Capable of multi-point distribution
  • TIA standard TIA-644
  • Maximum bitrate up to 3Gbit/s