As speeds get into the nanoseconds, creating single-ended sub-nanosecond edge rates becomes problematic when using large output swings (such as 3V or 5V).

i = c × ΔV/ΔT starts to create peak currents into the ampere range as the edge rates (rise and fall times) get into the nanosecond range. These edges increase power consumption and can produce EMI and noise.

The time spent in rising or falling times between logic thresholds limits the maximum output transition time (speed).

To overcome these issues, the output swings were reduced to 800mV. The smaller output swing is easier for the output devices to generate, saves power, and also reduces radiated noise and increases the maximum speed.

Figure 2-10 ECL Output

Emitter Coupled Logic, or ECL, was developed in the early 1960's, and is the oldest of the high speed logic family. The drivers are low impedance emitter follower outputs that generate a typical 800mV output differential voltage. The output transistors are operated in the linear region and not saturated to provide the fastest response. The outputs are typically terminated with 50Ω to a termination voltage rail that is two volts less than the output supply. ECL devices are commonly terminated with -2V to -5.2V, creating a typical output swing of -0.9V to -1.8V. Because of the low value termination resistors, ECL is the highest power dissipation interface by far.

RSECL, or Reduced Swing ECL is similar to ECL, but reduces the swing to 400mV, but still requires a negative termination voltage.

Figure 2-11 RSPECL Termination

PECL, or Positive ECL eliminates the negative supplies and shifts the swings above ground for positive swings of +3.2V and +4V and maintains the 800mV differential.

LVPECL, or Low Voltage PECL is the same as PECL, but lowers the thresholds to +1.6V and +2.4V to allow for lower supply voltages.

RSPECL, or Reduced Swing PECL reduces the swing to 400mV.

The devices that can support the 400mV swing standards are the LMH7322 and LMH7324.