SLCA006 June   2025 LM339 , LM393 , LMH7322 , TL331 , TLV1812 , TLV1871 , TLV1872 , TLV3601 , TLV3604

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1Introduction
  5. 2Output Types
    1. 2.1 Open Collector or Open Drain
      1. 2.1.1 Selectable Open Collector or Open Emitter Output
    2. 2.2 Push-Pull
      1. 2.2.1 Push-Pull with Separate Supplies
    3. 2.3 Differential
      1. 2.3.1 Differential Push Pull
      2. 2.3.2 ECL, RSECL, PECL, RSPECL, and LVPECL
      3. 2.3.3 Low Voltage Differential Signaling
      4. 2.3.4 Current Mode Logic
  6. 3Summary
  7. 4References

2.3.4 Current Mode Logic

Current Mode Logic (CML) is a switched-current output, similar to LVDS, but utilized at higher speeds. The termination is normally 50Ω on each output to the positive output termination voltage (VCCO) at the receiver.

The CML differential output swing and common mode voltage is not standardized, and can range from 400mV to 800mV differential. At speeds above 6Gbit/s, the differential is commonly reduced to 400mV.

The output stage consists of two 50Ω resistors to the output supply voltage with two associated switching transistors and a shared current source, as shown in Figure 2-14.

CML Output Figure 2-14 CML Output

One output transistor is conducting at a time, depending on the desired output state. The on transistor passes the 16mA through the corresponding 50Ω resistor creating a 50Ω/16mA=800mV voltage difference between the output and VCCO.

The other 50Ω resistor acts as a pull-up resistor and pull's the respective output to VCCO as no current is flowing through the resistor.

Because the load termination lines present a parallel 50Ω load to each output, the output swing is now half, or 400mV below VCCO at the receiver.

For CML output, please see the TLV3901 (Preliminary - contact Sales).

Table 2-8 Advantages and Disadvantages of CML Outputs
Advantages Disadvantages
  • Up to 12Gbit/s or more
  • User selectable differential voltage (reduces crosstalk and EMI)
  • Directly interfaces with matched impedance lines
  • High common mode rejection
  • Balanced lines reduce radiated EMI
  • Can be AC coupled
  • Requires two external 50Ω pull-up resistors
  • Only supports point-to-point
  • Higher power dissipation than LVDS
  • No defined standard - output thresholds can vary between manufacturers