SLDA060 March   2023 AM68 , AM68A , LP8733 , TPS62870 , TPS62871 , TPS62872 , TPS62873 , TPSM8287A12 , TPSM8287A15

 

  1.   Abstract
  2.   Trademarks
  3. 1Introduction
  4. 2PDN Selection Guide
  5. 3LP87334E PMIC Settings
  6. 4Example Power Maps
    1. 4.1 AM68x Single LP87334E PDN-6K, Base Features Only
    2. 4.2 AM68x Single LP87334E PDN-6J, Base and eFuse Programming
    3. 4.3 AM68x Single LP87334E PDN-6H, Base, eFuse and SD Card
    4. 4.4 AM68x Single LP87334E PDN-6G, Base, eFuse, SD Card, and USB2.0
  7. 5Conclusion
  8. 6References

2 PDN Selection Guide

Selecting a AM68x power design begins with answering a few end product questions:

  1. What is the desired market segment (automotive, industrial)?
  2. What is the desired operational temperature range?
  3. What is the desired MCU processing mode (MCU Island or Extended MCU)?
  4. What are the desired optional features?
    1. Low-power modes: MCU Only, DDR Retention, GPIO Retention
    2. Key functions: UHS-1 SD card, USB2.0 signaling, HS SoC eFuse programming

When a system’s desired features are determined, the PDN selection guide enables identification of a recommended power design. All recommended PDN designs provide:

  1. Processor peak power demands for full entitlement operation
  2. Base power resources to supply all voltages and controls needed for the SoC platform (SoC, LPDDR, Flash, power devices)
  3. Flexibility to trade off BOM cost and PCB area vs. optional features

A PDN design that groups MCU and Main supplies into common power rails can reduce a total number of power resources, BOM cost, PDN routing and PCB area. A grouped PDN supports Extended MCU processor operations that combines SoC Main and MCU processing resources. A grouped PDN will not provide a board design with FFI across power rails or MCU Island processing. One example of a grouped MCU and Main power solution is the J721S2 PDN-6x scheme that uses a LP87334E PMIC. Table 2-1 shows the PDN-6x base feature set supported by the base power resources and common across all variants. Table 2-2 shows all optional features available across the four PDN-6x (x = G, H, J, K) variants.

A PDN design that isolates MCU and Main supplies into independent power rails is needed to enable MCU Island processing and MCU Only low power mode. Independent MCU and Main power rails provides a board design with Freedom From Interference (FFI) across power rails for more robust systems. An isolated PDN typically requires more power resources that increases BOM cost, PDN routing and PCB area. For comparison, the J721S2 EVM SOM board (J721S2XSOMG01EVM) uses a J721S2 Dual TPS6594-Q1 and LP8764-Q1 PDN-0A scheme with isolated MCU and Main supplies. This J721S2 PDN-0A also supports up to ASIL-D functional safety capability, automotive qualified devices and a full feature set (base + all optional). A list of all optional features supported by J721S2 PDN-0A follows:

  • Three low power modes (MCU Only, DDR Retention, GPIO Retention),
  • Three key functions (UHS-I SD card, USB2.0 signaling, HS SoC eFuse programming
Table 2-1 PDN-6x Base Feature Set for Non-Safe, Grouped Design
Base FeaturesPDN-6x (all variants)
SafetyNone
MCU and Main suppliesGrouped
MCU operationsExtended MCU
Power Resource PNsLP87334E, TPS6287xZ0, TPS62850x
SoC / Pwr Devices TJ ranges [C]-40 to +105 / -40 to +125
SoC Clk [GHz]< 2

SDRAM Memory EMIF / Bank Qty:

SDRAM Memory Type (size, max rate):

2 EMIFs / Dual Banks

LPDDR4 (64 Gb/each, 4266 MTs)

Boot (size) Flash Memory:

Storage (size) Flash Memory:

OSPI (512Mb) or HyperFlash (1 Gb and 128 MB)

eMMC (16GB)

MCU I/O Signal Levels:

Main I/O Signal Levels:

Dual 1.8/3.3 V

Dual 1.8/3.3 V

Table 2-2 PDN-6x Optional Features per Variant for Non-Safe, Grouped Design
Optional FeaturesPDN-6GPDN-6H SK-AM68 Processor Starter KitPDN-6JPDN-6K
Low Power ModesNoneNoneNoneNone
Key Functions

HS SoC Efuse Prgm,

UHS-I SD Card,

USB2.0 interface

HS SoC Efuse Prgm,

UHS-I SD Card

HS SoC Efuse Prgm

None

Power Resource PNs2x TLV73318P,

TPS61240,

TLV7103318

TLV73318P,

TPS61240,

TLV7103318

TLV73318P

Pwr IC Cost Ratio

1.00.990.850.83

Pwr IC Area Ratio

Actual Area [mm^2]

1.0

68.2

0.87

59.0

0.82

55.7

0.68

46.5