SSTXP/N, SSRXP/N, RX1P/N, RX2PN, TX1P/N, and TX2P/N pairs should be routed with controlled 90-Ω differential impedance (±10%).
DP[3:0]P/N pairs should be routed with controlled 90-Ω differential impedance (±10%).
There is no inter-pair length match requirement between SSTXP/N and SSRXP/N.
Inter-pair matching between DP lanes (DP[3:0]) from GPU through TUSB1146 to the USB-C receptacle should be kept to less than 100 mils.
Keep away from other high speed signals.
Intra-pair routing (between P and N) should be kept to less than 5 mils.
Length matching should be near the location of mismatch.
Each pair should be separated at least by 3 times the signal trace width.
The use of bends in differential traces should be kept to a minimum. When bends are used, the number of left and right bends should be as equal as possible and the angle of the bend should be ≥ 135 degrees. This will minimize any length mismatch causes by the bends and therefore minimize the impact bends have on EMI.
Route all differential pairs on the same of layer.
The number of vias should be kept to a minimum. It is recommended to keep the vias count to 2 or less.
Keep traces on layers adjacent to ground plane.
Do not route differential pairs over any plane split.
Adding Test points will cause impedance discontinuity, and therefore, negatively impact signal performance. If test points are used, they should be placed in series and symmetrically. They must not be placed in a manner that causes a stub on the differential pair.
Highly recommended to have reference plane void under USB-C receptacle's super speed pins to minimize the capacitance effect of the receptacle.
Highly recommended to have reference plane void under the AC coupling capacitances.