SLLSFB2A April   2020  – June 2026 TUSB1146

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4  TUSB1146 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings
    3. 5.3  Recommended Operating Conditions
    4. 5.4  Thermal Information
    5. 5.5  Power Supply Characteristics
    6. 5.6  Control I/O DC Electrical Characteristics
    7. 5.7  USB and DP Electrical Characteristics
    8. 5.8  DCI Electrical Characteristics
    9. 5.9  Timing Requirements
    10. 5.10 Switching Characteristics
    11. 5.11 Typical Characteristics
  7. 6 Parameter Measurement Information
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 USB 3.1
      2. 7.3.2 DisplayPort
      3. 7.3.3 4-level Inputs
      4. 7.3.4 Receiver Linear Equalization
    4. 7.4 Device Functional Modes
      1. 7.4.1 Device Configuration in GPIO Mode
      2. 7.4.2 Device Configuration In I2C Mode
      3. 7.4.3 DisplayPort Mode
      4. 7.4.4 Linear EQ Configuration
      5. 7.4.5 VOD modes
        1. 7.4.5.1 Linearity VOD
        2. 7.4.5.2 Limited VOD
      6. 7.4.6 Transmit Equalization
      7. 7.4.7 USB3.1 Modes
      8. 7.4.8 Downstream Facing Port Adaptive Equalization
        1. 7.4.8.1 Fast Adaptive Equalization in I2C Mode
        2. 7.4.8.2 Full Adaptive Equalization
    5. 7.5 Programming
      1. 7.5.1 Transition between Modes
      2. 7.5.2 Pseudocode Examples
        1. 7.5.2.1 Fast AEQ with linear redriver mode
        2. 7.5.2.2 Fast AEQ with limited redriver mode
        3. 7.5.2.3 Full AEQ with linear redriver mode
        4. 7.5.2.4 Full AEQ with limited redriver mode
      3. 7.5.3 TUSB1146 I2C Address Options
      4. 7.5.4 TUSB1146 I2C Slave Behavior
  9. 8 Registers
    1. 8.1 Register Maps
      1. 8.1.1 TUSB1146 Registers
        1. 8.1.1.1  General_1 Register (Offset = 0xA) [reset = 0x1]
        2. 8.1.1.2  DCI_TXEQ_CTRL Register (Offset = 0xB) [reset = 0x6C]
        3. 8.1.1.3  DP01EQ_SEL Register (Offset = 0x10) [reset = 0x0]
        4. 8.1.1.4  DP23EQ_SEL Register (Offset = 0x11) [reset = 0x0]
        5. 8.1.1.5  DisplayPort_1 Register (Offset = 0x12) [reset = 0x0]
        6. 8.1.1.6  DisplayPort_2 Register (Offset = 0x13) [reset = 0x0]
        7. 8.1.1.7  AEQ_CONTROL1 Register (Offset = 0x1C) [reset = 0xF0]
        8. 8.1.1.8  AEQ_CONTROL2 Register (Offset = 0x1D) [reset = 0x20]
        9. 8.1.1.9  AEQ_LONG Register (Offset = 0x1E) [reset = 0x77]
        10. 8.1.1.10 USBC_EQ Register (Offset = 0x20) [reset = 0x0]
        11. 8.1.1.11 SS_EQ Register (Offset = 0x21) [reset = 0x0]
        12. 8.1.1.12 USB3_MISC Register (Offset = 0x22) [reset = 0x44]
        13. 8.1.1.13 USB_STATUS Register (Offset = 0x24) [reset = 0x41]
        14. 8.1.1.14 VOD_CTRL Register (Offset = 0x32) [reset = 0x40]
        15. 8.1.1.15 AEQ_STATUS Register (Offset = 0x3B) [reset = 0x0]
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 USB and DP Upstream Facing Port (USB Host / DP GPU to USB-C receptacle) Configuration
        2. 9.2.2.2 USB Downstream Facing Port (USB-C receptacle to USB Host) Configuration
          1. 9.2.2.2.1 Fixed Equalization
          2. 9.2.2.2.2 Fast Adaptive Equalization
          3. 9.2.2.2.3 Full Adaptive Equalization
      3. 9.2.3 Application Curve
    3. 9.3 System Examples
      1. 9.3.1 USB 3.1 Only
      2. 9.3.2 USB 3.1 and 2 Lanes of DisplayPort
      3. 9.3.3 DisplayPort Only
  11. 10Power Supply Recommendations
  12. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  13. 12Device and Documentation Support
    1. 12.1 Receiving Notification of Documentation Updates
    2. 12.2 Support Resources
    3. 12.3 Trademarks
    4. 12.4 Electrostatic Discharge Caution
    5. 12.5 Glossary
  14. 13Revision History
  15. 14Mechanical, Packaging, and Orderable Information

8.1.1.13 USB_STATUS Register (Offset = 0x24) [reset = 0x41]

USB_STATUS is shown in Table 8-15.

Return to the Summary Table.

Table 8-15 USB_STATUS Register Field Descriptions
Bit Field Type Reset Description
7 USB_FASTAEQ_STAT RH 0x0

When AEQ_EN = 1 and AEQ_MODE = x0, this status field indicates whether short or long EQ setting is used. When AEQ_EN = 0, this field will always default to 0h.

0x0 = Short channel EQ used.

0x1 = Long channel EQ used.
6 USB_AEQDONE_STAT RH 0x1

This field is low while AEQ is active and high when it is done. It is valid when U0_STAT and AEQ_EN = 1 or when FORCE_AEQ_EN = 1 and HW has reset FORCE_AEQ back to 0.

0x0 = AEQ is running

0x1 = AEQ is done
5 AEQ_HC_OVERFLOW RH 0x0

13-bit AEQ hit counter overflow status
4 RESERVED R 0x0

Reserved
3 CM_ACTIVE RH 0x0

Compliance mode status.

0x0 = Not in USB3.1 compliance mode.

0x1 = In USB3.1 compliance mode.
2 U0_STAT RH 0x0

U0 Status. Set if enters U0 state.
1 U2U3_STAT RH 0x0

U2/U3 Status. Set if enters U2/U3 state.
0 DISC_STAT RH 0x1

Disconnect Status. Set if enters Disconnect state.