SLLSFB2A April   2020  – June 2026 TUSB1146

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4  TUSB1146 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings
    3. 5.3  Recommended Operating Conditions
    4. 5.4  Thermal Information
    5. 5.5  Power Supply Characteristics
    6. 5.6  Control I/O DC Electrical Characteristics
    7. 5.7  USB and DP Electrical Characteristics
    8. 5.8  DCI Electrical Characteristics
    9. 5.9  Timing Requirements
    10. 5.10 Switching Characteristics
    11. 5.11 Typical Characteristics
  7. 6 Parameter Measurement Information
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 USB 3.1
      2. 7.3.2 DisplayPort
      3. 7.3.3 4-level Inputs
      4. 7.3.4 Receiver Linear Equalization
    4. 7.4 Device Functional Modes
      1. 7.4.1 Device Configuration in GPIO Mode
      2. 7.4.2 Device Configuration In I2C Mode
      3. 7.4.3 DisplayPort Mode
      4. 7.4.4 Linear EQ Configuration
      5. 7.4.5 VOD modes
        1. 7.4.5.1 Linearity VOD
        2. 7.4.5.2 Limited VOD
      6. 7.4.6 Transmit Equalization
      7. 7.4.7 USB3.1 Modes
      8. 7.4.8 Downstream Facing Port Adaptive Equalization
        1. 7.4.8.1 Fast Adaptive Equalization in I2C Mode
        2. 7.4.8.2 Full Adaptive Equalization
    5. 7.5 Programming
      1. 7.5.1 Transition between Modes
      2. 7.5.2 Pseudocode Examples
        1. 7.5.2.1 Fast AEQ with linear redriver mode
        2. 7.5.2.2 Fast AEQ with limited redriver mode
        3. 7.5.2.3 Full AEQ with linear redriver mode
        4. 7.5.2.4 Full AEQ with limited redriver mode
      3. 7.5.3 TUSB1146 I2C Address Options
      4. 7.5.4 TUSB1146 I2C Slave Behavior
  9. 8 Registers
    1. 8.1 Register Maps
      1. 8.1.1 TUSB1146 Registers
        1. 8.1.1.1  General_1 Register (Offset = 0xA) [reset = 0x1]
        2. 8.1.1.2  DCI_TXEQ_CTRL Register (Offset = 0xB) [reset = 0x6C]
        3. 8.1.1.3  DP01EQ_SEL Register (Offset = 0x10) [reset = 0x0]
        4. 8.1.1.4  DP23EQ_SEL Register (Offset = 0x11) [reset = 0x0]
        5. 8.1.1.5  DisplayPort_1 Register (Offset = 0x12) [reset = 0x0]
        6. 8.1.1.6  DisplayPort_2 Register (Offset = 0x13) [reset = 0x0]
        7. 8.1.1.7  AEQ_CONTROL1 Register (Offset = 0x1C) [reset = 0xF0]
        8. 8.1.1.8  AEQ_CONTROL2 Register (Offset = 0x1D) [reset = 0x20]
        9. 8.1.1.9  AEQ_LONG Register (Offset = 0x1E) [reset = 0x77]
        10. 8.1.1.10 USBC_EQ Register (Offset = 0x20) [reset = 0x0]
        11. 8.1.1.11 SS_EQ Register (Offset = 0x21) [reset = 0x0]
        12. 8.1.1.12 USB3_MISC Register (Offset = 0x22) [reset = 0x44]
        13. 8.1.1.13 USB_STATUS Register (Offset = 0x24) [reset = 0x41]
        14. 8.1.1.14 VOD_CTRL Register (Offset = 0x32) [reset = 0x40]
        15. 8.1.1.15 AEQ_STATUS Register (Offset = 0x3B) [reset = 0x0]
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 USB and DP Upstream Facing Port (USB Host / DP GPU to USB-C receptacle) Configuration
        2. 9.2.2.2 USB Downstream Facing Port (USB-C receptacle to USB Host) Configuration
          1. 9.2.2.2.1 Fixed Equalization
          2. 9.2.2.2.2 Fast Adaptive Equalization
          3. 9.2.2.2.3 Full Adaptive Equalization
      3. 9.2.3 Application Curve
    3. 9.3 System Examples
      1. 9.3.1 USB 3.1 Only
      2. 9.3.2 USB 3.1 and 2 Lanes of DisplayPort
      3. 9.3.3 DisplayPort Only
  11. 10Power Supply Recommendations
  12. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  13. 12Device and Documentation Support
    1. 12.1 Receiving Notification of Documentation Updates
    2. 12.2 Support Resources
    3. 12.3 Trademarks
    4. 12.4 Electrostatic Discharge Caution
    5. 12.5 Glossary
  14. 13Revision History
  15. 14Mechanical, Packaging, and Orderable Information

5.6 Control I/O DC Electrical Characteristics

over operating free-air temperature range (unless otherwise noted)
PARAMETERTEST CONDITIONSMINTYPMAXUNIT
4-level Inputs
4-Level VTHThreshold 0 / RVCC = 3.3 V0.55V
4-Level VTHThreshold R/ FloatVCC = 3.3 V1.65V
4-Level VTHThreshold Float / 1VCC33 = 3.3 V2.7V
IIHHigh level input currentVCC = 3.6 V; VIN = 3.6 V2060µA
IILLow level input currentVCC = 3.6 V; VIN = 0 V–100-40µA
RPUInternal pull-up resistance48kΩ
RPDInternal pull-down resistance98kΩ
2-State CMOS Input (CTL0, CTL1, FLIP). CTL0 and FLIP are Failsafe.
VIHHigh-level input voltageVCC = 3.0V23.6V
VILLow-level input voltageVCC = 3.6V00.8V
RPDInternal pull-down resistance for HPDIN, CADSNK400500600kΩ
RPDInternal pull-down resistance for CTL1300400500kΩ
IIH_CTL1High-level input current for CTL1VIN = 3.6 V–1111µA
IIL_CTL1Low-level input current for CTL1VIN = GND, VCC = 3.6 V–11µA
IIH_HPD_CADHigh-level input current for HPDIN, CADSNKVIN = 3.6 V–1111µA
IIL_HPD_CADLow-level input current for HPDIN, CADSNKVIN = GND, VCC = 3.6 V–11µA
IIH_CTL0_FLIPHigh-level input current for CTL0 and FLIPVIN = 3.6 V; I2C_EN = 0–11µA
IIL_CTL0_FLIPLow-level input current for CTL0 and FLIPVIN = GND, VCC = 3.6 V; I2C_EN = 0;–11µA
I2C Control Pins (SCL, SDA)
VIH_3p3VHigh-level input voltage when configured for 3.3V I2C levelI2C_EN = 12.03.6V
VIL_3p3VLow-level input voltage when configured for 3.3V I2C levelI2C_EN = 100.8V
VIH_1p8VHigh-level input voltage when configured for 1.8V I2C levelI2C_EN = F1.2V
VIL_1p8VLow-level input voltage when configured for 1.8V I2C levelI2C_EN = F00.6V
VOLLow-level output voltageI2C_EN = 0; IOL = 6 mA00.4V
IOLLow-level output currentI2C_EN = 0; VOL = 0.4 V20mA
II(I2C)Input current0.1 x V(I2C) < Input voltage < 3.3 V–11µA
CI(I2C)Input capacitance10pF
C(I2C_FM+_BUS)I2C bus capacitance for FM+ (1MHz)150pF
C(I2C_FM_BUS)I2C bus capacitance for FM (400kHz)150pF
R(EXT_I2C_FM+)External resistors on both SDA and SCL when operating at FM+ (1MHz)C(I2C_FM+_BUS) = 150 pF620820910Ω
R(EXT_I2C_FM)External resistors on both SDA and SCL when operating at FM (400kHz)C(I2C_FM_BUS) = 150 pF62015002200Ω