SLLSFN5B June   2023  – September 2025 ISO1228

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings
    3. 5.3  Recommended Operating Conditions
    4. 5.4  Thermal Information
    5. 5.5  Power Ratings
    6. 5.6  Insulation Specifications
    7. 5.7  Safety-Related Certifications
    8. 5.8  Safety Limiting Values
    9. 5.9  Electrical Characteristics—DC Specification
    10. 5.10 Switching Characteristics—AC Specification
    11. 5.11 Typical Characteristics
  7. 6 Parameter Measurement Information
    1. 6.1 Test Circuits
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Surge Protection
      2. 7.3.2  Field Side LED Indication
      3. 7.3.3  Serial and Parallel Output option
      4. 7.3.4  Cyclic Redundancy Check (CRC)
      5. 7.3.5  FAULT Indication
      6. 7.3.6  Digital Low Pass Filter
      7. 7.3.7  SPI Register Map
      8. 7.3.8  SPI Timing - Non-Daisy Chain
      9. 7.3.9  SPI Timing - Daisy Chain
      10. 7.3.10 SPI Timing - Burst Mode
    4. 7.4 Device Functional Modes
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Sinking Type Digital Inputs
      2. 8.2.2 Sourcing Type Digital Inputs
      3. 8.2.3 Sink/Source Type Digital Inputs
      4. 8.2.4 Design Requirements
        1. 8.2.4.1 Detailed Design Procedure
          1. 8.2.4.1.1 Current Limit
          2. 8.2.4.1.2 Voltage Thresholds
          3. 8.2.4.1.3 Wire-Break Detection
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Documentation Support
      1. 9.1.1 Related Documentation
    2. 9.2 Receiving Notification of Documentation Updates
    3. 9.3 Support Resources
    4. 9.4 Trademarks
    5. 9.5 Electrostatic Discharge Caution
    6. 9.6 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

5.6 Insulation Specifications

PARAMETER TEST CONDITIONS VALUE UNIT
DW-16
CLR External clearance(1) Shortest terminal-to-terminal distance through air 4 mm
CPG External creepage(1) Shortest terminal-to-terminal distance across the package surface 4 mm
DTI Distance through the insulation Minimum internal gap (internal clearance) >17 µm
CTI Comparative tracking index DIN EN 60112 (VDE 0303-11); IEC 60112 >400 V
Material group According to IEC 60664-1 II
Overvoltage category per IEC 60664-1 Rated mains voltage ≤ 150VRMS I-IV
Overvoltage category per IEC 60664-1 Rated mains voltage ≤ 300VRMS I-III
DIN EN IEC 60747-17 (VDE 0884-17)(2)
VIORM Maximum repetitive peak isolation voltage AC voltage (bipolar) 637 VPK
VIOWM Maximum working isolation voltage AC voltage; Time dependent dielectric breakdown (TDDB) Test; 450 VRMS
DC voltage 637 VDC
VIOTM Maximum transient isolation voltage VTEST = VIOTM, t = 60s (qualification);
VTEST = 1.2 × VIOTM, t = 1s (100% production)		 4242 VPK
VIMP Maximum impulse voltage(3) Tested in air, 1.2/50-µs waveform per IEC 62368-1 4000 VPK
VIOSM Maximum surge isolation voltage(4) VIOSM ≥ 1.3 x VIMP; Tested in oil (qualification test),
1.2/50μs waveform per IEC 62368-1		 5200 VPK
qpd Apparent charge(5) Method a, After Input-output safety test subgroup 2/3,
Vini = VIOTM, tini = 60s;
Vpd(m) = 1.2 × VIORM, tm = 10s		 ≤5 pC
Method a, After environmental tests subgroup 1,
Vini = VIOTM, tini = 60s;
Vpd(m) = 1.2 × VIORM, tm = 10s		 ≤5
Method b: At routine test (100% production);
Vini = 1.2 × VIOTM, tini = 1s;
Vpd(m) = 1.5 × VIORM, tm = 1s (method b1) or 
Vpd(m) = Vini, tm = tini (method b2)		 ≤5
CIO Barrier capacitance, input to output(6) VIO = 0.4 × sin (2πft), f = 1MHz ≅0.5 pF
RIO Isolation resistance(6) VIO = 500V, TA = 25°C > 1012 Ω
VIO = 500V, 100°C ≤ TA ≤ 125°C > 1011
VIO = 500V at TS = 150°C > 109
Pollution degree 2
Climatic category 40/125/21
UL 1577
VISO Maximum withstanding isolation voltage VTEST = VISO , t = 60s (qualification),
VTEST = 1.2 × VISO , t = 1s (100% production)		 3000 VRMS
(1) Creepage and clearance requirements should be applied according to the specific equipment isolation standards of an application. Care should be taken to maintain the creepage and clearance distance of a board design to ensure that the mounting pads of the isolator on the printed-circuit board do not reduce this distance. Creepage and clearance on a printed-circuit board become equal in certain cases. Techniques such as inserting grooves and/or ribs on a printed-circuit board are used to help increase these specifications.
(2) This isolated digital input is suitable for basic electrical insulation only within the safety ratings. Compliance with the safety ratings shall be ensured by means of suitable protective circuits.
(3) Testing is carried out in air to determine the surge immunity of the package.
(4) Testing is carried out in oil to determine the intrinsic surge immunity of the isolation barrier.
(5) Apparent charge is electrical discharge caused by a partial discharge (pd).
(6) All pins on each side of the barrier tied together creating a two-terminal device.