SLLSFY0A September   2025  – December 2025 TCAN843-Q1

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings
    3. 5.3  ESD Ratings - IEC Specifications
    4. 5.4  Recommended Operating Conditions
    5. 5.5  Thermal Information
    6. 5.6  Power Dissipation Ratings
    7. 5.7  Power Supply Characteristics
    8. 5.8  Electrical Characteristics
    9. 5.9  Timing Requirements
    10. 5.10 Switching Characteristics
    11. 5.11 Typical Characteristics
  7. 6 Parameter Measurement Information
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Supply Pins
        1. 7.3.1.1 VSUP Pin
        2. 7.3.1.2 VCC Pin
        3. 7.3.1.3 VIO Pin
      2. 7.3.2 Digital Inputs and Outputs
        1. 7.3.2.1 TXD Pin
        2. 7.3.2.2 RXD Pin
        3. 7.3.2.3 nFAULT Pin
        4. 7.3.2.4 EN Pin
        5. 7.3.2.5 nSTB Pin
        6. 7.3.2.6 NC Pin
      3. 7.3.3 GND
      4. 7.3.4 INH Pin
      5. 7.3.5 WAKE Pin
      6. 7.3.6 CAN Bus Pins
      7. 7.3.7 Faults
        1. 7.3.7.1 Internal and External Fault Indicators
          1. 7.3.7.1.1 Power-Up (PWRON Flag)
          2. 7.3.7.1.2 Wake-Up Request (WAKERQ Flag)
          3. 7.3.7.1.3 Undervoltage Faults
            1. 7.3.7.1.3.1 Undervoltage on VSUP
            2. 7.3.7.1.3.2 Undervoltage on VCC
            3. 7.3.7.1.3.3 Undervoltage on VIO
          4. 7.3.7.1.4 TXD Dominant State Timeout (TXDDTO Flag)
          5. 7.3.7.1.5 TXD Shorted to RXD Fault (TXDRXD Flag)
          6. 7.3.7.1.6 CAN Bus Dominant Fault (CANDOM Flag)
      8. 7.3.8 Local Faults
        1. 7.3.8.1 TXD Dominant Timeout (TXD DTO)
        2. 7.3.8.2 Thermal Shutdown (TSD)
        3. 7.3.8.3 Undervoltage Lockout (UVLO)
        4. 7.3.8.4 Unpowered Devices
        5. 7.3.8.5 Floating Terminals
        6. 7.3.8.6 CAN Bus Short-Circuit Current Limiting
    4. 7.4 Device Functional Modes
      1. 7.4.1 Operating Mode Description
        1. 7.4.1.1 Normal Mode
        2. 7.4.1.2 Silent Mode
        3. 7.4.1.3 Standby Mode
        4. 7.4.1.4 Go-To-Sleep Mode
        5. 7.4.1.5 Sleep Mode
          1. 7.4.1.5.1 Remote Wake Request via Wake-Up Pattern (WUP)
          2. 7.4.1.5.2 Local Wake-Up (LWU) by WAKE Input Terminal
      2. 7.4.2 CAN Transceiver
        1. 7.4.2.1 CAN Transceiver Operation
          1. 7.4.2.1.1 Driver and Receiver Function Tables
          2. 7.4.2.1.2 CAN Bus States
  9. 8 Application Information Disclaimer
    1. 8.1 Application Information
      1. 8.1.1 Typical Application
      2. 8.1.2 Design Requirements
        1. 8.1.2.1 Bus Loading, Length and Number of Nodes
      3. 8.1.3 Detailed Design Procedure
        1. 8.1.3.1 CAN Termination
      4. 8.1.4 Application Curves
    2. 8.2 Power Supply Recommendations
    3. 8.3 Layout
      1. 8.3.1 Layout Guidelines
      2. 8.3.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Documentation Support
      1. 9.1.1 CAN Transceiver Physical Layer Standards:
    2. 9.2 Receiving Notification of Documentation Updates
    3. 9.3 Support Resources
    4. 9.4 Trademarks
    5. 9.5 Electrostatic Discharge Caution
    6. 9.6 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

5.10 Switching Characteristics

Over recommended operating conditions with TJ = -40°C to 150°C, unless otherwise noted. All typical values are taken at 25°C, VSUP = 12V, VIO = 3.3V, VCC = 5V and RL = 60Ω
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Driver Characteristics
tpHR Propagation delay time, high TXD to driver recessive RL = 60Ω, CL = 100pF, RCM = open 90 ns
tpLD Propagation delay time, low TXD to driver dominant 75 ns
tsk(p) Pulse skew (|tpHR - tpLD|) 25 ns
tR Differential output signal rise time 45 ns
tF Differential output signal fall time 45 ns
tTXDDTO Dominant timeout TXD = 0V, RL = 60Ω, CL = open 1.2 3.8 ms
Receiver Characteristics
tpRH Propagation delay time, bus recessive input to high RXD CL(RXD) = 15pF 65 ns
tpDL Propagation delay time, bus dominant input to RXD low output 60 ns
tR Output signal rise time (RXD) 10 ns
tF Output signal fall time (RXD) 10 ns
tBUSDOM Dominant time out RL = 60Ω, CL = open 1.2 3.8 ms
CAN FD Characteristics
tΔBIT(BUS)(1) Transmitted recessive bit width variation on CAN bus output pins with tBIT(TXD) = 500ns RL = 60Ω, CL = 100pF, CL_RXD = 15pF
tΔBit(BUS) = tBIT(BUS) - tBIT(TXD)		 -65 30 ns
tΔBIT(BUS)(1) Transmitted recessive bit width variation on CAN bus output pins with tBIT(TXD) = 200ns RL = 60Ω, CL = 100pF, CL_RXD = 15pF
tΔBit(BUS) = tBIT(BUS) - tBIT(TXD)		 -45 10 ns
tΔBIT(RXD)(1) Received recessive bit width variation on RXD output pins with tBIT(TXD) = 500ns RL = 60Ω, C2 = 100pF, CL_RXD = 15pF
tΔBit(RXD) = tBIT(RXD) - tBIT(TXD)		 -100 50 ns
tΔBIT(RXD)(1) Received recessive bit width variation on RXD output pins with tBIT(TXD) = 200ns RL = 60Ω, C2 = 100pF, CL_RXD = 15pF
tΔBit(RXD) = tBIT(RXD) - tBIT(TXD)		 -80 20 ns
tΔREC(1) Receiver timing symmetry with tBIT(TXD) = 500ns RL = 60Ω, C2 = 100pF, CL_RXD = 15pF
ΔtREC = tBIT(RXD) - tBIT(BUS)		 –65 40 ns
Receiver timing symmetry with tBIT(TXD) = 200ns RL = 60Ω, C2 = 100pF, CL_RXD = 15pF
ΔtREC = tBIT(RXD) - tBIT(BUS)		 –45 15 ns
(1) The input signal on TXD shall have rise times and fall times (10% to 90%) of less than 10ns