SLLSG07 March   2025 TUSB1044A

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Timing Requirements
    7. 5.7 Switching Characteristics
    8. 5.8 Typical Characteristics
  7. 6 Parameter Measurement Information
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 USB 3.2
      2. 7.3.2 USB 3.2 x2 Description
      3. 7.3.3 DisplayPort
      4. 7.3.4 4-Level Inputs
      5. 7.3.5 Receiver Linear Equalization
    4. 7.4 Device Functional Modes
      1. 7.4.1 Device Configuration in GPIO Mode
      2. 7.4.2 Device Configuration in I2C Mode
      3. 7.4.3 DisplayPort Mode
      4. 7.4.4 Custom Alternate Mode
      5. 7.4.5 Linear EQ Configuration
      6. 7.4.6 Adjustable VOD Linear Range and DC Gain
      7. 7.4.7 USB3.1 Modes
    5. 7.5 Programming
      1. 7.5.1 Procedure to Write to TUSB1044A I2C Registers:
      2. 7.5.2 Procedure to Read the TUSB1044A I2C Registers:
      3. 7.5.3 Procedure to Set a Starting Sub-Address for I2C Reads:
  9. 8 Register Maps
    1. 8.1 TUSB1044A Registers
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 ESD Protection
      4. 9.2.4 Application Curve
    3. 9.3 System Examples
      1. 9.3.1 USB 3.2 only (USB/DP Alternate Mode)
      2. 9.3.2 USB3.2 and 2 Lanes of DisplayPort
      3. 9.3.3 DisplayPort Only
      4. 9.3.4 USB 3.2 Only (USB/Custom Alternate Mode)
      5. 9.3.5 USB3.2 and 1 Lane of Custom Alt Mode
      6. 9.3.6 USB3.2 and 2 Lanes of Custom Alt Mode
      7. 9.3.7 USB3.2 and 4 Lanes of Custom Alt Mode
    4. 9.4 Power Supply Recommendations
    5. 9.5 Layout
      1. 9.5.1 Layout Guidelines
      2. 9.5.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Documentation Support
      1. 10.1.1 Related Documentation
    2. 10.2 Receiving Notification of Documentation Updates
    3. 10.3 Support Resources
    4. 10.4 Trademarks
    5. 10.5 Electrostatic Discharge Caution
    6. 10.6 Glossary
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information

8.1 TUSB1044A Registers

Table 8-1 lists the memory-mapped registers for the TUSB1044A registers. All register offset addresses not listed in Table 8-1 should be considered as reserved locations and the register contents should not be modified.

Table 8-1 TUSB1044A Registers
OffsetAcronymRegister NameSection
AhGeneral_1General Registers 1Go
BhGeneral_2General Registers 2Go
ChGeneral_3General Registers 3Go
10hUFP2_EQUFP2 EQ ControlGo
11hUFP1_EQUFP1 EQ ControlGo
12hDisplayPort_1AUX Snoop StatusGo
13hDisplayPort_2DP Lane Enable/Disable ControlGo
20hDFP2_EQDFP2 EQ ControlGo
21hDFP1_EQDFP1 EQ ControlGo
22hUSB3_MISCMisc USB3 ControlsGo
23hUSB3_LOSUSB3 LOS Threshold ControlsGo

Complex bit access types are encoded to fit into small table cells. Table 8-2 shows the codes that are used for access types in this section.

Table 8-2 TUSB1044A Access Type Codes
Access TypeCodeDescription
Read Type
RRRead
RHR
H		Read
Set or cleared by hardware
Write Type
WWWrite
WSWWrite
Reset or Default Value
-nValue after reset or the default value

8.1.1 General_1 Register (Offset = Ah) [Reset = 00h]

General_1 is shown in Table 8-3.

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Table 8-3 General_1 Register Field Descriptions
BitFieldTypeResetDescription
7RESERVEDR0h Reserved
6USB32_BY2_ENR/W0hSet this field to enable USB3.2 x2 mode. USB3.2 x2 mode allows the device to operate up to 20Gbps. When this field is zero, the device is limited to 10Gbps
0h = USB3.2 x2 disable
1h = USB3.2 x2 enable
5SWAP_SELR/W0hSet this field to perform a global direction swap on all the channels.
0h = Channel directions and EQ settings are in normal mode
1h = Reverse all channel directions and EQ settings for the input ports.
4EQ_OVERRIDER/W0hSet this field to allow the software to use the EQ settings from registers instead of values sampled from pins.
0h = EQ settings based on sampled state of EQ pins.
1h = EQ settings based on the programmed value of each of the EQ registers.
3HPDIN_OVERRIDER/W0h Overrides the HPDIN pin state.
0h = HPD_IN based on HPD_IN pin.
1h = HPD_IN high.
2FLIP_SELR/W0h FLIPSEL
0h = Normal Orientation
1h = Flip orientation.
1-0CTLSEL_1:0R/W0h Controls the DP and USB modes.
0h = Disabled. All RX and TX for USB3 and DisplayPort are disabled.
1h = USB3.2 only enabled.
2h = Four Lanes of DisplayPort enabled.
3h = USB3.2 and Two DisplayPort Lanes.

8.1.2 General_2 Register (Offset = Bh) [Reset = 00h]

General_2 is shown in Table 8-4.

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Table 8-4 General_2 Register Field Descriptions
BitFieldTypeResetDescription
7-4RESERVEDR0h Reserved
3-0CH_SWAP_SELR/W0h Swaps direction (TX to RX and RX to TX) and EQ settings of individual channels. Channels are numbered from 0 to 3. One bit per lane.
0h = Channel and EQ settings normal.
1h = Reverse channel direction and EQ setting.

8.1.3 General_3 Register (Offset = Ch) [Reset = 00h]

General_3 is shown in Table 8-5.

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Table 8-5 General_3 Register Field Descriptions
BitFieldTypeResetDescription
7RESERVEDR0h Reserved
6VOD_DCGAIN_OVERRIDER/W0h Set this field to allow the software to use the VOD linearity range and DC gain settings from registers instead of value sampled from pins
0h = VOD linearity and DC gain settings based on sampled CFG[2:1] pins. 1b = EQ settings based on programmed value of each VOD linearity and DC Gain registers.
5-2VOD_DCGAIN_SELR/W0hThis field selects the VOD linearity range and DC gain for all the channels and in all directions. When VOD_DCGAIN_OVERRIDE = 0b, this field reflects the sampled state of CFG[1:0] pins. When VOD_DCGAIN_OVERRIDE = 1b, software can change the VOD linearity range and DC gain for all the channels and in all directions based on the value written to this field. Each CFG is a 2-bit value. The register-to-CFG1/0 mapping is: [5:2] = {CFG1[1:0], CFG0[1:0]} where CFGx[1:0] mapping is:
0h = 0
1h = R
2h = F
3h = 1
1-0DIR_SELR/W0h Sets the operation mode. If this field is 2h or 3h and CTLSEL[1:0] is 3h, then device functions as USB3.2 x2.
0h = USB + DP Alt Mode Source
1h = USB + DP Alt Mode Sink.
2h = USB + Custom or USB3.2x2 source
3h = USB + Custom or USB3.2x2 Sink.

8.1.4 UFP2_EQ Register (Offset = 10h) [Reset = 00h]

UFP2_EQ is shown in Table 8-6.

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Table 8-6 UFP2_EQ Register Field Descriptions
BitFieldTypeResetDescription
7-4UTX2EQ_SELR/W0h Field selects the EQ for the UTX2P/N pins. When EQ_OVERRIDE = 0b, this field reflects the sampled state of UEQ[1:0] pins. When EQ_OVERRIDE = 1b, the software can change the EQ setting for the UTX2P/N pins based on the value written to this field.
3-0URX2EQ_SELR/W0h Field selects the EQ for the URX2P/N pins. When EQ_OVERRIDE = 0b, this field reflects the sampled state of UEQ[1:0] pins. When EQ_OVERRIDE = 1b, the software can change the EQ setting for the URX2P/N pins based on the value written to this field.

8.1.5 UFP1_EQ Register (Offset = 11h) [Reset = 00h]

UFP1_EQ is shown in Table 8-7.

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Table 8-7 UFP1_EQ Register Field Descriptions
BitFieldTypeResetDescription
7-4UTX1EQ_SELR/W0h Field selects the EQ for the UTX1P/N pins. When EQ_OVERRIDE = 0b, this field reflects the sampled state of UEQ[1:0] pins. When EQ_OVERRIDE = 1b, the software can change the EQ setting for the UTX1P/N pins based on the value written to this field.
3-0URX1EQ_SELR/W0h Field selects the EQ for the URX1P/N pins. When EQ_OVERRIDE = 0b, this field reflects the sampled state of UEQ[1:0] pins. When EQ_OVERRIDE = 1b, the software can change the EQ setting for the URX1P/N pins based on the value written to this field.

8.1.6 DisplayPort_1 Register (Offset = 12h) [Reset = 00h]

DisplayPort_1 is shown in Table 8-8.

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Table 8-8 DisplayPort_1 Register Field Descriptions
BitFieldTypeResetDescription
7RESERVEDR0h Reserved
6-5SET_POWER_STATERH0h This field represents the snooped value of the AUX write to DPCD address 0x00600. When AUX_SNOOP_DISABLE = 0b, the enable/disable of DP lanes based on the snooped value. When AUX_SNOOP_DISABLE = 1b, then DP lane enable/disable are determined by state of DPx_DISABLE registers, where x = 0, 1, 2, or 3. This field is reset to 0h by hardware when CTLSEL1 changes from a 1b to a 0b.
4-0LANE_COUNT_SETRH0h This field represents the snooped value of AUX write to DPCD address 0x00101 register. When AUX_SNOOP_DISABLE = 0b, DP lanes enabled specified by the snoop value. Unused DP lanes are disabled to save power. When AUX_SNOOP_DISABLE = 1b, then DP lanes enable/disable are determined by DPx_DISABLE registers, where x = 0, 1, 2, or 3. This field is reset to 0h by hardware when CTLSEL1 changes from a 1b to a 0b.

8.1.7 DisplayPort_2 Register (Offset = 13h) [Reset = 00h]

DisplayPort_2 is shown in Table 8-9.

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Table 8-9 DisplayPort_2 Register Field Descriptions
BitFieldTypeResetDescription
7AUX_SNOOP_DISABLER/W0h Controls whether the DP lanes are enabled based on AUX snooped value or registers.
0h = AUX snoop enabled.
1h = AUX snoop disabled. DP lanes are controlled by registers.
6RESERVEDR0h Reserved
5-4AUX_SBU_OVRR/W0h This field overrides the AUXP/N to SBU1/2 connect and disconnect based on CTL1 and FLIP. Change this field to 1b to allow traffic to pass through AUX to SBU regardless of the state of CTLSEL1 and FLIPSEL register.
0h = AUX to SBU connection determined by CTLSEL1 and FLIPSEL
1h = AUXP -> SBU1 and AUXN -> SBU2
2h = AUXP -> SBU2 and AUXN -> SBU1
3h = AUX to SBU open.
3DP3_DISABLER/W0h When AUX_SNOOP_DISABLE = 1b, this field can be used to enable or disable DP lane 3. When AUX_SNOOP_DISABLE = 0b, changes to this field have no effect on lane 3 functionality.
0h = DP Lane 3 enabled.
1h = DP Lane 3 disabled.
2DP2_DISABLER/W0h When AUX_SNOOP_DISABLE = 1b, this field can be used to enable or disable DP lane 2. When AUX_SNOOP_DISABLE = 0b, changes to this field have no effect on lane 2 functionality.
0h = DP Lane 2 enabled.
1h = DP Lane 2 disabled.
1DP1_DISABLER/W0h When AUX_SNOOP_DISABLE = 1b, this field can be used to enable or disable DP lane 1. When AUX_SNOOP_DISABLE = 0b, changes to this field have no effect on lane 1 functionality.
0h = DP Lane 1 enabled.
1h = DP Lane 1 disabled.
0DP0_DISABLER/W0h When AUX_SNOOP_DISABLE = 1b, this field can be used to enable or disable DP lane 0. When AUX_SNOOP_DISABLE = 0b, changes to this field have no effect on lane 0 functionality.
0h = DP Lane 0 enabled.
1h = DP Lane 0 disabled.

8.1.8 DFP2_EQ Register (Offset = 20h) [Reset = 00h]

DFP2_EQ is shown in Table 8-10.

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Table 8-10 DFP2_EQ Register Field Descriptions
BitFieldTypeResetDescription
7-4DTX2EQ_SELR/W0h Field selects the EQ for the DTX2P/N pins. When EQ_OVERRIDE = 0b, this field reflects the sampled state of DEQ[1:0] pins. When EQ_OVERRIDE = 1b, the software can change the EQ setting for the DTX2P/N pins based on the value written to this field.
3-0DRX2EQ_SELR/W0h Field selects the EQ for the DRX2P/N pins. When EQ_OVERRIDE = 0b, this field reflects the sampled state of DEQ[1:0] pins. When EQ_OVERRIDE = 1b, the software can change the EQ setting for the DRX2P/N pins based on the value written to this field.

8.1.9 DFP1_EQ Register (Offset = 21h) [Reset = 00h]

DFP1_EQ is shown in Table 8-11.

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Table 8-11 DFP1_EQ Register Field Descriptions
BitFieldTypeResetDescription
7-4DTX1EQ_SELR/W0h Field selects the EQ for the DTX1P/N pins. When EQ_OVERRIDE = 0b, this field reflects the sampled state of DEQ[1:0] pins. When EQ_OVERRIDE = 1b, the software can change the EQ setting for the DTX1P/N pins based on the value written to this field.
3-0DRX1EQ_SELR/W0h Field selects the EQ for the DRX1P/N pins. When EQ_OVERRIDE = 0b, this field reflects the sampled state of DEQ[1:0] pins. When EQ_OVERRIDE = 1b, the software can change the EQ setting for the DRX1P/N pins based on the value written to this field.

8.1.10 USB3_MISC Register (Offset = 22h) [Reset = 04h]

USB3_MISC is shown in Table 8-12.

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Table 8-12 USB3_MISC Register Field Descriptions
BitFieldTypeResetDescription
7CM_ACTIVERH0h Compliance mode status.
0h = Not in USB3.2 compliance mode.
1h = In USB3.2 compliance mode.
6LFPS_EQR/W0h Controls whether the EQ settings based on URX[2:1]EQ_SEL, UTX[2:1]EQ_SEL, DRX[2:1]EQ_SEL, and DTX[2:1]EQ_SEL applies to the received LFPS signal.
0h = EQ set to 0 when receiving LFPS
1h = EQ set by the related registers when receiving LFPS.
5U2U3_LFPS_DEBOUNCER/W0h Controls whether or not incoming LFPS is debounced or not.
0h = No debounce of LFPS before U2/U3 exit.
1h = 200us debounce of LFPS before U2/U3 exit.
4DISABLE_U2U3_RXDETR/W0h Controls whether or not Rx.Detect is performed in U2/U3 state.
0h = Rx.Detect in U2/U3 enabled.
1h = Rx.Detect in U2/U3 disabled.
3-2DFP_RXDET_INTERVALR/W1h This field controls the Rx.Detect interval for the downstream facing port (DTX1P/N and DTX2P/N).
0h = 8ms
1h = 12ms
2h = Reserved
3h = Reserved.
1-0USB_COMPLIANCE_CTRLR/W0h Controls whether compliance mode is determined by FSM or register.
0h = Compliance mode determined by FSM.
1h = Compliance mode enabled in DFP direction.
2h = Compliance mode enabled in UFP direction.
3h = Compliance mode disabled.

8.1.11 USB3_LOS Register (Offset = 23h) [Reset = 23h]

USB3_LOS is shown in Table 8-13.

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Table 8-13 USB3_LOS Register Field Descriptions
BitFieldTypeResetDescription
7VCM_LFPS_WAITR/W0h Add delay for TX VCM to settle before passing LFPS
0h = Enable
1h = Disable
6RESERVEDR0h Reserved
5-3CFG_LOS_HYSTR/W4h Controls LOS hysteresis defined as 20 log (LOS deassert threshold/LOS assert threshold).
0h = 0.15dB
1h = 0.85dB
2h = 1.45dB
3h = 2.00dB
4h = 2.70dB
5h = 3.00dB
6h = 3.40dB
7h = 3.80dB
2-0CFG_LOS_VTHR/W3h Controls LOS assert threshold voltage
0h = 67mV
1h = 72mV
2h = 79mV
3h = 85mV
4h = 91mV
5h = 97mV
6h = 105mV
7h = 112mV