SLLSG07 March   2025 TUSB1044A

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Timing Requirements
    7. 5.7 Switching Characteristics
    8. 5.8 Typical Characteristics
  7. 6 Parameter Measurement Information
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 USB 3.2
      2. 7.3.2 USB 3.2 x2 Description
      3. 7.3.3 DisplayPort
      4. 7.3.4 4-Level Inputs
      5. 7.3.5 Receiver Linear Equalization
    4. 7.4 Device Functional Modes
      1. 7.4.1 Device Configuration in GPIO Mode
      2. 7.4.2 Device Configuration in I2C Mode
      3. 7.4.3 DisplayPort Mode
      4. 7.4.4 Custom Alternate Mode
      5. 7.4.5 Linear EQ Configuration
      6. 7.4.6 Adjustable VOD Linear Range and DC Gain
      7. 7.4.7 USB3.1 Modes
    5. 7.5 Programming
      1. 7.5.1 Procedure to Write to TUSB1044A I2C Registers:
      2. 7.5.2 Procedure to Read the TUSB1044A I2C Registers:
      3. 7.5.3 Procedure to Set a Starting Sub-Address for I2C Reads:
  9. 8 Register Maps
    1. 8.1 TUSB1044A Registers
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 ESD Protection
      4. 9.2.4 Application Curve
    3. 9.3 System Examples
      1. 9.3.1 USB 3.2 only (USB/DP Alternate Mode)
      2. 9.3.2 USB3.2 and 2 Lanes of DisplayPort
      3. 9.3.3 DisplayPort Only
      4. 9.3.4 USB 3.2 Only (USB/Custom Alternate Mode)
      5. 9.3.5 USB3.2 and 1 Lane of Custom Alt Mode
      6. 9.3.6 USB3.2 and 2 Lanes of Custom Alt Mode
      7. 9.3.7 USB3.2 and 4 Lanes of Custom Alt Mode
    4. 9.4 Power Supply Recommendations
    5. 9.5 Layout
      1. 9.5.1 Layout Guidelines
      2. 9.5.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Documentation Support
      1. 10.1.1 Related Documentation
    2. 10.2 Receiving Notification of Documentation Updates
    3. 10.3 Support Resources
    4. 10.4 Trademarks
    5. 10.5 Electrostatic Discharge Caution
    6. 10.6 Glossary
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information

5.5 Electrical Characteristics

over operating free-air temperature and voltage range (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Power
PUSB-ACTIVE Average power when configured for USB 3.2x1 only mode. Link in U0 with GEN2 data transmission;  EQ control pins = NC; K28.5 pattern at 10Gbps; VID = 1000mVp-p;  VOD Linearity = 900mVp-p; CTL1 = L; CTL0 = H 297 mW
PUSB-DP-ACTIVE Average power when configured for USB 3.2x1 and 2 lane DP. Link in U0 with GEN2 data transmission and DP active;  EQ control pins = NC; K28.5 pattern at 10Gbps; VID = 1000mVp-p;  VOD Linearity = 900mVp-p;  CTL1 = H; CTL0 = H 578 mW
PCUSTOM-ACTIVE Average power when configured for USB 3.2x2 Link in U0 with GEN2 data transmission;  EQ control pins = NC; K28.5 pattern at 10Gbps; VID = 1000mVp-p;  VOD Linearity = 900mVp-p; 578 mW
PCUSTOM-ACTIVE Average power when configured for USB 3.2x1 and 2 channel custom alt mode. Link in U0 with GEN2 data transmission and custom alt mode active;  EQ control pins = NC; K28.5 pattern at 10Gbps; VID = 1000mVp-p;  VOD Linearity = 900mVp-p;  CTL1 = H; CTL0 = H 578 mW
P4DP-ACTIVE Average power when configured for Four DP lanes Four active DP lanes;  EQ control pins = NC; K28.5 pattern at 10Gbps; VID = 1000mVp-p;  VOD Linearity = 900mVp-p;  CTL1 = H; CTL0 = L 564 mW
PUSB-NC Average power when configured for USB3.2x1 only and nothing connected to TXP/N pins. No USB device connected;  CTL1 = L; CTL0 = H 2.5 mW
PUSB-U2U3 Average power when configured for USB3.2x1 only and link in U2 or U3 state. Link in U2 or U3 state;  CTL1 = L; CTL0 = H 2 mW
PSHUTDOWN Average power when device in Shutdown CTL1 = L; CTL0 = L; I2C_EN = 0; 0.65 mW
4-State CMOS Inputs(UEQ[1:0];DEQ[1:0], CFG[1:0], A[1:0], I2C_EN, VIO_SEL)
IIH High-level input current VCC = 3.6V; VIN = 3.6V 20 80 µA
IIL Low-level input current VCC = 3.6V; VIN = 0V –160 –40 µA
4-Level VTH Threshold 0 / R VCC = 3.3V 0.55 V
Threshold R/ Float VCC = 3.3V 1.65 V
Threshold Float / 1 VCC = 3.3V 2.7 V
RPU Internal pullup resistance 46 kΩ
RPD Internal pulldown resistance 95 kΩ
2-State CMOS Input (CTL0, CTL1, FLIP, HPDIN, SLP_S0#, SWAP, DIR[1:0]).
VIH-3.3V High-level input voltage VCC = 3.3V; VIO_SEL = "0" or "R"; 2 3.6 V
VIL-3.3V Low-level input voltage VCC = 3.3V; VIO_SEL = "0" or "R"; 0 0.8 V
VIH-1.8V High-level input voltage VCC = 3.3V; VIO_SEL = "F" or "1"; 1.2 3.6 V
VIL-1.8V Low-level input voltage VCC = 3.3V; VIO_SEL = "F" or "1"; 0 0.4 V
RPD_CTL1 Internal pulldown resistance for CTL1, CTL0, DIR0, DIR1, FLIP, SLP_S0# 500 kΩ
RPD_HPDIN Internal pulldown resistance for HPDIN 400 kΩ
RPD_SWAP Internal pulldown resistance for SWAP 200 kΩ
IIH High-level input current VIN = 3.6V –25 25 µA
IIL Low-level input current VIN = GND, VCC = 3.6V –25 25 µA
I2C Control Pins SCL, SDA
VIH-3.3V High-level input voltage VCC = 3.3V; VIO_SEL = "0" or "F"; I2C Mode Enabled; 2 3.6 V
VIL-3.3V Low-level input voltage VCC = 3.3V; VIO_SEL = "0" or "F"; I2C Mode Enabled; 0 0.8 V
VIH-1.8V High-level input voltage VCC = 3.3V; VIO_SEL = "R" or "1"; I2C Mode Enabled; 1.2 3.6 V
VIL-1.8V Low-level input voltage VCC = 3.3V; VIO_SEL = "R" or "1"; I2C Mode Enabled; 0 0.4 V
VOL Low-level output voltage I2C_EN ! = "0"; IOL = 3mA 0 0.4 V
IOL Low-level output current I2C_EN ! = "0"; VOL = 0.4V 20 mA
II_I2C Input current on SDA pin 0.1 × VI2C < Input voltage < 3.3V –10 10 µA
Ci_I2C Input capacitance 0.5 5 pF
USB Gen 2 Differential Receiver (UTX1P/N, UTX2P/N, DRX1P/N, DRX2P/N)
VRX-DIFF-PP Input differential peak-peak voltage swing  dynamic range AC-coupled differential peak-to-peak signal measured post CTLE through a reference channel 2000 mVpp
VRX-DC-CM Common-mode voltage bias in the receiver (DC) 0 V
RRX-DIFF-DC Differential input impedance (DC) Present after a GEN 2 device is detected on TXP/TXN 72 120 Ω
RRX-CM-DC Receiver DC common-mode impedance Present after a GEN 2 device is detected on TXP/TXN 18 30 Ω
ZRX-HIGH-IMP-DC-POS Common-mode input impedance with termination disabled (DC) Present when no GEN 2 device is detected on TXP/TXN. Measured over the range of 0V to 500mV with respect to GND. 25 kΩ
VSIGNAL-DET-DIFF-PP Input differential peak-to-peak signal detect assert level 10Gbps PRBS7 pattern; low loss input channel; 80 mV
VRX-IDLE-DET-DIFF-PP Input differential peak-to-peak signal detect deassert level 10Gbps PRBS7 pattern; low loss input channel; 60 mV
VRX-LFPS-DET-DIFF-PP Low-frequency Periodic Signaling (LFPS) Detect Threshold Below the minimum is squelched. 100 300 mV
CRX RX input capacitance to GND At 5GHz 0.3 pF
RLRX-DIFF Differential return loss 50MHz to 2.5GHz at 90Ω –13 dB
RLRX-DIFF Differential return loss 5GHz at 90Ω –12 dB
RLRX-CM Common-mode return loss 50MHz to 5GHz at 90Ω –10.5 dB
EQSSP Receiver equalization at maximum setting UEQ[1:0] and DEQ[1:0] at 5GHz. 10 dB
USB Gen 2 Differential Transmitter (DTX1P/N, DTX2P/N, URX1P/N, URX2P/N)
VTX-DIFF-PP Transmitter dynamic differential voltage swing range 1500 mVpp
VTX-RCV-DETECT Amount of voltage change allowed during Receiver Detection At 3.3V 600 mV
VTX-CM-IDLE-DELTA Transmitter idle common-mode voltage change while in U2/U3 and not actively transmitting LFPS measured at the connector side of the AC coupling caps with 50Ω load –600 600 mV
VTX-DC-CM Common-mode voltage bias in the transmitter (DC) 1.75 2.3 V
VTX-CM-AC-PP-ACTIVE Tx AC common-mode voltage active Rx EQ setting matches input channel loss; Max mismatch from Txp + Txn for both time and amplitude; –40℃ to 85℃; 100 mVpp
VTX-IDLE-DIFF-AC-PP AC electrical idle differential peak-to-peak output voltage At package pins 0 10 mV
VTX-IDLE-DIFF-DC DC electrical idle differential output voltage At package pins after low-pass filter to remove AC component 0 14 mV
RTX-DIFF Differential impedance of the driver 75 120 Ω
CAC-COUPLING AC coupling capacitor 75 265 nF
RTX-CM Common-mode impedance of the driver Measured with respect to AC ground over 0V to 500mV 18 30 Ω
ITX-SHORT TX short circuit current TX + /- shorted to GND 74 mA
RLTX-DIFF Differential return loss 50MHz to 2.5GHz at 90Ω –13 dB
RLTX-DIFF Differential return loss 5GHz at 90Ω –10.5 dB
RLTX-CM Common-mode return loss 50MHz to 5GHz at 90Ω –10 dB
AC Characteristics
Crosstalk Differential cross talk between TX and RX signal pairs At 5GHz -30 dB
GLF Low-frequency voltage gain for 0dB setting. At 100MHz; 200mVpp < VID < 2000mVpp; 0dB DC Gain; –1 0 1 dB
CP1 dB-LF-1100 Low-frequency –1dB compression point At 100MHz; 200 mVpp < VID < 2000 mVpp; 1100mVpp linearity setting; 1100 mVpp
CP1 dB-HF-1100 High-frequency –1dB compression point At 5GHz; 200mVpp < VID < 2000 mVpp; 1100mVpp linearity setting; 1200 mVpp
fLF Low-frequency cutoff 200mVpp < VID < 2000mVpp 22 50 kHz
DJ TX output deterministic jitter 200mVpp < VID < 2000mVpp, PRBS7, 10Gbps 0.07 UIpp
DJ TX output deterministic jitter 200mVpp < VID < 2000mVpp, PRBS7, 8.1Gbps 0.07 UIpp
TJ TX output total jitter 200mVpp < VID < 2000mVpp, PRBS7, 10Gbps 0.11 UIpp
TJ TX output total jitter 200 mVpp < VID < 2000 mVpp, PRBS7, 8.1Gbps 0.11 UIpp
DisplayPort Receiver (UTX1P/N, UTX2P/N, URX1P/N, URX2P/N)
VID_PP Peak-to-peak input differential dynamic voltage range 1500 V
VIC Input common-mode voltage 0 V
CAC AC coupling capacitance 75 265 nF
EQDP Receiver equalizer DPEQ1, DPEQ0 at 4.05GHz 9.5 dB
dR Data rate UHBR10 10.0 Gbps
Rti Input Termination resistance 80 100 120 Ω
DisplayPort Transmitter (DTX1P/N, DTX2P/N, DRX1P/N, DRX2P/N)
VTX-DIFFPP VOD dynamic range 1500 mV
AUXP/N and SBU1/2
RON Output ON resistance VCC = 3.3V; VI = 0V to 0.4V for AUXP; VI = 2.7V to 3.6V for AUXN 5 12 Ω
ΔRON ON resistance mismatch within pair VCC = 3.3V; VI = 0V to 0.4V for AUXP; VI = 2.7V to 3.6V for AUXN 2.0 Ω
RON_FLAT ON resistance flatness (RON max – RON min) measured at identical VCC and temperature VCC = 3.3V; VI = 0V to 0.4V for AUXP; VI = 2.7V to 3.6V for AUXN 1.0 Ω
VAUXP_DC_CM AUX Channel DC common-mode voltage for AUXP and SBU1. VCC = 3.3V 0 0.4 V
VAUXN_DC_CM AUX Channel DC common-mode voltage for AUXN and SBU2 VCC = 3.3V 2.7 3.6 V