SLLSG07 March   2025 TUSB1044A

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Timing Requirements
    7. 5.7 Switching Characteristics
    8. 5.8 Typical Characteristics
  7. 6 Parameter Measurement Information
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 USB 3.2
      2. 7.3.2 USB 3.2 x2 Description
      3. 7.3.3 DisplayPort
      4. 7.3.4 4-Level Inputs
      5. 7.3.5 Receiver Linear Equalization
    4. 7.4 Device Functional Modes
      1. 7.4.1 Device Configuration in GPIO Mode
      2. 7.4.2 Device Configuration in I2C Mode
      3. 7.4.3 DisplayPort Mode
      4. 7.4.4 Custom Alternate Mode
      5. 7.4.5 Linear EQ Configuration
      6. 7.4.6 Adjustable VOD Linear Range and DC Gain
      7. 7.4.7 USB3.1 Modes
    5. 7.5 Programming
      1. 7.5.1 Procedure to Write to TUSB1044A I2C Registers:
      2. 7.5.2 Procedure to Read the TUSB1044A I2C Registers:
      3. 7.5.3 Procedure to Set a Starting Sub-Address for I2C Reads:
  9. 8 Register Maps
    1. 8.1 TUSB1044A Registers
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 ESD Protection
      4. 9.2.4 Application Curve
    3. 9.3 System Examples
      1. 9.3.1 USB 3.2 only (USB/DP Alternate Mode)
      2. 9.3.2 USB3.2 and 2 Lanes of DisplayPort
      3. 9.3.3 DisplayPort Only
      4. 9.3.4 USB 3.2 Only (USB/Custom Alternate Mode)
      5. 9.3.5 USB3.2 and 1 Lane of Custom Alt Mode
      6. 9.3.6 USB3.2 and 2 Lanes of Custom Alt Mode
      7. 9.3.7 USB3.2 and 4 Lanes of Custom Alt Mode
    4. 9.4 Power Supply Recommendations
    5. 9.5 Layout
      1. 9.5.1 Layout Guidelines
      2. 9.5.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Documentation Support
      1. 10.1.1 Related Documentation
    2. 10.2 Receiving Notification of Documentation Updates
    3. 10.3 Support Resources
    4. 10.4 Trademarks
    5. 10.5 Electrostatic Discharge Caution
    6. 10.6 Glossary
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information

7.3.2 USB 3.2 x2 Description

The TUSB1044A configured for USB 3.2 x2 mode determines if the link is operating in USB 3.2 x2 or in USB 3.2 x1. If the link is USB 3.2 x2, then TUSB1044A operates with one port operating as a USB 3.2 x1 port and the remaining port following the lead of the other port. The port functioning as a USB 3.2 x1 port is called the config lane. The determination of the config lane is based solely on the Type-C orientation. For normal orientation (FLIP = L), Port 1 is the config lane. For the flipped orientation (FLIP = H), Port 2 is the config lane.

In USB 3.2 x2, the config lane operates as a standard USB 3.2 x1 port. While in all USB low power states (Disconnect, U1, U2, and U3), the non-config lane is disabled to conserve power. Entry to and exit from these low power states is determined solely by the config lane. If the config lane detects an exit from a low power state, then the non-config is enabled.

Table 7-1 Config Lane Selection
DIR0 PIN OR DIR0 REGISTERFLIP PIN OR FLIP_SEL REGISTERCONFIG LANENON-CONFIG LANE
0 (source)0DRX1 -> URX1DRX2 -> URX2
UTX1 -> DTX1UTX2 -> DTX2
1DRX2 -> URX2DRX1 -> URX1
UTX2 -> DTX2UTX1 -> DTX1
1 (sink)0DRX2 -> URX2DRX1 -> URX1
UTX2 -> DTX2UTX1 -> DTX1
1DRX1 -> URX1DRX2 -> URX2
UTX1 -> DTX1UTX2 -> DTX2
Note:

In GPIO mode the TUSB1044A is enabled for USB3.2 x2 mode when all the following conditions are true: DIR1 pin = H, DIR0 pin = L or H, CTL0 pin = H and CTL1 pin = H.

In I2C mode, USB3.2 x2 mode is disabled by default. USB3.2x2 in I2C mode is enabled if either of the following conditions is true:

  • At offset 0xA, USB32_BY2_EN bit = 1'b1 and CTLSEL_1:0 bits = 2'b01.
  • At offset 0xA, CTLSEL_1:0 bits = 2'b11, and at offset 0xC, DIR_SEL bits = 2'b10 or 2'b11