SLLSG07 March   2025 TUSB1044A

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Timing Requirements
    7. 5.7 Switching Characteristics
    8. 5.8 Typical Characteristics
  7. 6 Parameter Measurement Information
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 USB 3.2
      2. 7.3.2 USB 3.2 x2 Description
      3. 7.3.3 DisplayPort
      4. 7.3.4 4-Level Inputs
      5. 7.3.5 Receiver Linear Equalization
    4. 7.4 Device Functional Modes
      1. 7.4.1 Device Configuration in GPIO Mode
      2. 7.4.2 Device Configuration in I2C Mode
      3. 7.4.3 DisplayPort Mode
      4. 7.4.4 Custom Alternate Mode
      5. 7.4.5 Linear EQ Configuration
      6. 7.4.6 Adjustable VOD Linear Range and DC Gain
      7. 7.4.7 USB3.1 Modes
    5. 7.5 Programming
      1. 7.5.1 Procedure to Write to TUSB1044A I2C Registers:
      2. 7.5.2 Procedure to Read the TUSB1044A I2C Registers:
      3. 7.5.3 Procedure to Set a Starting Sub-Address for I2C Reads:
  9. 8 Register Maps
    1. 8.1 TUSB1044A Registers
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 ESD Protection
      4. 9.2.4 Application Curve
    3. 9.3 System Examples
      1. 9.3.1 USB 3.2 only (USB/DP Alternate Mode)
      2. 9.3.2 USB3.2 and 2 Lanes of DisplayPort
      3. 9.3.3 DisplayPort Only
      4. 9.3.4 USB 3.2 Only (USB/Custom Alternate Mode)
      5. 9.3.5 USB3.2 and 1 Lane of Custom Alt Mode
      6. 9.3.6 USB3.2 and 2 Lanes of Custom Alt Mode
      7. 9.3.7 USB3.2 and 4 Lanes of Custom Alt Mode
    4. 9.4 Power Supply Recommendations
    5. 9.5 Layout
      1. 9.5.1 Layout Guidelines
      2. 9.5.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Documentation Support
      1. 10.1.1 Related Documentation
    2. 10.2 Receiving Notification of Documentation Updates
    3. 10.3 Support Resources
    4. 10.4 Trademarks
    5. 10.5 Electrostatic Discharge Caution
    6. 10.6 Glossary
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information

7.4.7 USB3.1 Modes

The TUSB1044A monitors the physical layer conditions like receiver termination, electrical idle, LFPS, and SuperSpeed signaling rate to determine the state of the USB3.1 interface. Depending on the state of the USB 3.1 interface, the TUSB1044A can be in one of four primary modes of operation when USB 3.1 is enabled (CTL0 = H or CTLSEL0 = 1b1): Disconnect, U2/U3, U1, and U0.

The disconnect mode is the state in which TUSB1044A has not detected far-end termination on both upstream facing port (UFP) or downstream facing port (DFP). The disconnect mode is the lowest power mode of each of the four modes. The TUSB1044A remains in this mode until far-end receiver termination has been detected on both UFP and DFP. The TUSB1044A immediately exits this mode and enters U0 mode when far-end termination is detected.

When in U0 mode, the TUSB1044A redrives all traffic received on UFP and DFP. U0 is the highest power mode of all USB3.1 modes. The TUSB1044A remains in U0 mode until electrical idle occurs on both UFP and DFP. Upon detecting electrical idle, the TUSB1044A immediately transitions to U1.

The U1 mode is the intermediate mode between U0 mode and U2/U3 mode. In U1 mode, the TUSB1044A UFP and DFP receiver termination remain enabled. The UFP and DFP transmitter DC common-mode voltage is maintained. The power consumption in U1 is similar to power consumption of U0.

Next to the disconnect mode, the U2 and U3 mode is next lowest power state. While in this mode, the TUSB1044A periodically performs far-end receiver detection. Anytime the far-end receiver termination is not detected on either UFP or DFP, the TUSB1044A leaves the U2 and U3 mode and transition to the disconnect mode. The device also monitors for a valid LFPS. Upon detection of a valid LFPS, the TUSB1044A immediately transitions to the U0 mode. In U2 and U3 mode, the TUSB1044A receiver terminations remains enabled, but the TX DC common-mode voltage is not maintained.

When SLP_S0# is asserted low, the TUSB1044A disables Receiver Detect functionality. While SLP_S0# is low and TUSB1044A is in U2 and U3, the TUSB1044A disables LOS and LFPS detection circuitry and RX termination for both channels remains enabled. This allows even lower TUSB1044A power consumption while in the U2 and U3 mode. When SLP_S0# is asserted high, the TUSB1044A again starts performing far-end receiver detection as well as monitors the LFPS so the device can know when to exit the U2 and U3 mode.

When SLP_S0# is asserted low and the TUSB1044A is in disconnect mode, the TUSB1044A remains in disconnect mode and never performs far-end receiver detection. This allows even lower TUSB1044A power consumption while in the disconnect mode. When SLP_S0# is asserted high, the TUSB1044A again starts performing far-end receiver detection so the device can know when to exit disconnect mode.