SLOA011B January 2018 – July 2021 LF347 , LF353 , LM348 , MC1458 , TL022 , TL061 , TL062 , TL071 , TL072 , UA741
It takes a finite time for a signal to propagate through the internal circuitry of an op amp. Therefore, it takes a certain period of time for the output to react to a step change in the input. Also the output normally overshoots the target value, experiences damped oscillation, and settles to a final value. Settling time, ts, is the time required for the output voltage to settle to within a specified percentage of the final value given a step input. Figure 5-13 shows this graphically.
Settling time is a design issue in data acquisition circuits when signals are changing rapidly. An example is when using an op amp following a multiplexer to buffer the input to an analog to digital converter. Step changes can occur at the input to the op amp when the multiplexer changes channels. The output of the op amp must settle to within a certain tolerance before the analog to digital converter samples the signal.