The TLV2711 is designed to provide better sinking and sourcing output currents than previous CMOS rail-to-rail output devices. This device is specified to sink 500 μA and source 250 μA at V_DD = 3 V and V_DD = 5 V at a maximum quiescent I_DD of 25 μA. These specifications provide a greater than 90% power efficiency.

When driving heavy dc loads, such as 10 kΩ, the positive edge under slewing conditions can experience some distortion; see also Figure 5-23. This condition is affected by three factors:

• Where the load is referenced. When the load is referenced to either rail, this condition does not occur. The distortion occurs only when the output signal swings through the point where the load is referenced. Figure 5-24 illustrates two 10-kΩ load conditions. The first load condition shows the distortion seen for a 10-kΩ load tied to 2.5 V. The third load condition shows no distortion for a 10-kΩ load tied to 0 V.
• Load resistance. As the load resistance increases, the distortion seen on the output decreases. Figure 5-24 illustrates the difference seen on the output for a 10-kΩ load and a 100-kΩ load with both tied to 2.5 V.
• Input signal edge rate. Faster input edge rates for a step input result in more distortion than with slower input edge rates.