SLOS887G September 2014 – May 2025 TMP112-Q1 , TMP112D-Q1
PRODUCTION DATA
The first byte transmitted by the controller is the target address with the R/W bit low. The TMP112-Q1/TMP112D-Q1 device then acknowledges reception of a valid address. The next byte transmitted by the controller is the pointer register. The TMP112-Q1/TMP112D-Q1 device then acknowledges reception of the pointer register byte. The next byte or bytes are written to the register addressed by the pointer register. The TMP112-Q1/TMP112D-Q1 device acknowledges reception of each data byte. The controller can terminate data transfer by generating a START or STOP condition.