SLUSC25B February 2015 – October 2026 TPS2388
PRODUCTION DATA
COMMAND = 14h with 1 Data Byte, Read/Write
Bit Descriptions:
Detection and classification enable for each port.
When in Manual mode, setting a bit means that only one cycle (detection or classification) is performed for the corresponding port. The bit is automatically cleared by the time the cycle has been completed.
Note that similar result can be obtained by writing to the Detect/Class Restart register.
It is also cleared if a port turn off (Power Enable register) is issued.
When in semiauto mode, as long as the port is kept off, detection and classification are performed continuously, as long as the class and detect enable bits are kept set, but the class will be done only if the detection was valid. A Detect/Class Restart PB command can also be used to set the CLEn and DETEn bits, if in semiauto mode.
During tOVLD, tLIM or tSTART cool down cycle, any Detect/Class Enable command for that port will be delayed until end of cool-down period. Note that at the end of cool down cycle, one or more detection/class cycles are automatically restarted as described previously, if the class and/or detect enable bits are set.
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| CLE4 | CLE3 | CLE2 | CLE1 | DETE4 | DETE3 | DETE2 | DETE1 |
| R/W-0 | R/W-0 | R/W-0 | R/W-0 | R/W-0 | R/W-0 | R/W-0 | R/W-0 |
| LEGEND: R/W = Read/Write; R = Read only; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 7–4 | CLE4-CLE1 | R/W | 0 | Classification enable bits. |
| 3–0 | DETE4-DETE1 | R/W | 0 | Detection enable bits. |