SLUSC25B February   2015  – October 2026 TPS2388

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
    1. 4.1 Detailed Pin Description
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Timing Requirements
    7. 5.7 Switching Characteristics
    8. 5.8 Typical Characteristics
  7. 6 Parameter Measurement Information
    1. 6.1 Timing Diagrams
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Port Remapping
      2. 7.3.2 Port Power Priority
      3. 7.3.3 A/D Converter
      4. 7.3.4 I2C Watchdog
      5. 7.3.5 Foldback Protection
    4. 7.4 Device Functional Modes
      1. 7.4.1 Port Operating Modes
        1. 7.4.1.1 Semiauto
        2. 7.4.1.2 Manual
        3. 7.4.1.3 Power Off
      2. 7.4.2 Detection
      3. 7.4.3 Classification
      4. 7.4.4 DC Disconnect
    5. 7.5 Programming
      1. 7.5.1 I2C Serial Interface
    6. 7.6 Register Maps
      1. 7.6.1  Complete Register Set
      2. 7.6.2  INTERRUPT Register
      3. 7.6.3  INTERRUPT MASK Register
      4. 7.6.4  POWER EVENT Register
      5. 7.6.5  DETECTION EVENT Register
      6. 7.6.6  FAULT EVENT Register
      7. 7.6.7  START/ILIM EVENT Register
      8. 7.6.8  SUPPLY EVENT Register
      9. 7.6.9  PORT 1 STATUS Register
      10. 7.6.10 PORT 2 STATUS Register
      11. 7.6.11 PORT 3 STATUS Register
      12. 7.6.12 PORT 4 STATUS Register
      13. 7.6.13 POWER STATUS Register
      14. 7.6.14 Pin Status Register
      15. 7.6.15 OPERATING MODE Register
      16. 7.6.16 DISCONNECT ENABLE Register
      17. 7.6.17 DETECT/CLASS ENABLE Register
      18. 7.6.18 Port Power Priority/ICUT Disable Register Name
      19. 7.6.19 TIMING CONFIGURATION Register
      20. 7.6.20 GENERAL MASK Register
      21. 7.6.21 DETECT/CLASS RESTART Register
      22. 7.6.22 POWER ENABLE Register
      23. 7.6.23 RESET Register
      24. 7.6.24 ID Register
      25. 7.6.25 Police 21 Configuration Register
      26. 7.6.26 Police 43 Configuration Register
      27. 7.6.27 IEEE Power Enable Register
      28. 7.6.28 Power-on Fault Register
      29. 7.6.29 PORT RE-MAPPING Register
      30. 7.6.30 Port 21 Multi Bit Priority Register
      31. 7.6.31 Port 43 Multi Bit Priority Register
      32. 7.6.32 TEMPERATURE Register
      33. 7.6.33 INPUT VOLTAGE Register
      34. 7.6.34 PORT 1 CURRENT Register
      35. 7.6.35 PORT 2 CURRENT Register
      36. 7.6.36 PORT 3 CURRENT Register
      37. 7.6.37 PORT 4 CURRENT Register
      38. 7.6.38 PORT 1 VOLTAGE Register
      39. 7.6.39 PORT 2 VOLTAGE Register
      40. 7.6.40 PORT 3 VOLTAGE Register
      41. 7.6.41 PORT 4 VOLTAGE Register
      42. 7.6.42 PoE Plus Register
      43. 7.6.43 FIRMWARE REVISION
      44. 7.6.44 I2C WATCHDOG Register
      45. 7.6.45 DEVICE ID Register
      46. 7.6.46 PORT 1 DETECT RESISTANCE Register
      47. 7.6.47 PORT 2 DETECT RESISTANCE Register
      48. 7.6.48 PORT 3 DETECT RESISTANCE Register
      49. 7.6.49 PORT 4 DETECT RESISTANCE Register
  9. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Introduction to PoE
      2. 8.1.2 TPS2388 Application
      3. 8.1.3 Kelvin Current Sensing Resistor
      4. 8.1.4 Connections on Unused Ports
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Power Pin Bypass Capacitors
        2. 8.2.2.2 Per Port Components
        3. 8.2.2.3 System Level Components (not shown in the schematic diagrams)
      3. 8.2.3 Application Curves
    3. 8.3 Power Supply Recommendations
      1. 8.3.1 VDD
      2. 8.3.2 VPWR
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
        1. 8.4.1.1 Port Current Kelvin Sensing
      2. 8.4.2 Layout Example
        1. 8.4.2.1 Component Placement and Routing Guidelines
          1. 8.4.2.1.1 Power Pin Bypass Capacitors
          2. 8.4.2.1.2 Per-Port Components
  10. 9 Device and Documentation Support
    1. 9.1 Receiving Notification of Documentation Updates
    2. 9.2 Support Resources
    3. 9.3 Trademarks
    4. 9.4 Electrostatic Discharge Caution
    5. 9.5 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

7.6.27 IEEE Power Enable Register

COMMAND = 23h with 1 Data Byte, Write Only

Used to do a port(s) turn on during semiauto mode. This command is ignored if in manual mode. Note that if at completion of this command the addressed port is not turned on, the corresponding bits in the Detect/Class Enable register (register 14h) are being set, which means that detection and classification are performed continuously, as long as the class and detect enable bits are kept set.

Writing a 1 at a TmPONn bit will turn on the associated port but only if the IEEE802.3 TPON timing specification can be met. TPON specification is the time from the completion of a valid detection cycle to port turn ON.

If TPON specification cannot be met, a new detection cycle is restarted, followed by a classification cycle, at the end of which the port is turned on, but only if a valid detection and classification is returned. For this case, there is no additional attempt to turn on the port until this push button is reasserted.

Note that a port turn on will be performed only after both its current detection and classification cycle are completed

Note that writing a 1 at T1PONn and T2PONn of same port during the same write operation is interpreted as a T1PONn.

The corresponding PGCn and PECn bits of Power Event register will also be set depending on the result, while the CLSCn and DETCn bits of Detection Event register will be set based on the result and the CLCHE and DECHE bits in the General Mask register.

Also note that tOVLD, tLIM, tSTART, and disconnect events are prioritary over the power on command. During tOVLD, tLIM, or tSTART cool down cycle, any port turn on using IEEE Power Enable command will be ignored and the port will be kept off.

Figure 7-31 IEEE Power Enable Register Format
76543210
Type 2 IEEE Power Enable PushbuttonType 1 IEEE Power Enable Pushbutton
T2PON4T2PON3T2PON2T2PON1T1PON4T1PON3T1PON2T1PON1
W-0W-0W-0W-0W-0W-0W-0W-0
LEGEND: R/W = Read/Write; R = Read only; W = Write only; -n = value after reset
Table 7-25 IEEE Power Enable Register Field Descriptions
BitFieldTypeResetDescription
7–4T2PON4T2PON1W0If class 4 is detected during the first event classification, a second event classification is performed. If the last detection result is not valid or last classification result yields “over current” or is different from the first classification event result, the port is not turned on, and the STRTn bit in Start/Ilim Event register is set, while the corresponding fault code in the Power-on Fault register is written.

When power-on is complete and if class 4 has been detected, the corresponding PoEPn bit in PoE Plus register is set and the value of the corresponding Police Configuration register is set to 640mA (08h code). This is done within 5ms of completion of inrush.

3–0T1PON4T1PON1W0Indicates only a single-event classification is performed, even if a class 4 PD is detected.

If the last detection result is not valid or last classification result yields “over current”, the port is not turned on, and the STRTn bit in Start/Ilim Event register is set, while the corresponding fault code in the Power-on Fault register is written.