SLUSC25B February   2015  – October 2026 TPS2388

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
    1. 4.1 Detailed Pin Description
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Timing Requirements
    7. 5.7 Switching Characteristics
    8. 5.8 Typical Characteristics
  7. 6 Parameter Measurement Information
    1. 6.1 Timing Diagrams
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Port Remapping
      2. 7.3.2 Port Power Priority
      3. 7.3.3 A/D Converter
      4. 7.3.4 I2C Watchdog
      5. 7.3.5 Foldback Protection
    4. 7.4 Device Functional Modes
      1. 7.4.1 Port Operating Modes
        1. 7.4.1.1 Semiauto
        2. 7.4.1.2 Manual
        3. 7.4.1.3 Power Off
      2. 7.4.2 Detection
      3. 7.4.3 Classification
      4. 7.4.4 DC Disconnect
    5. 7.5 Programming
      1. 7.5.1 I2C Serial Interface
    6. 7.6 Register Maps
      1. 7.6.1  Complete Register Set
      2. 7.6.2  INTERRUPT Register
      3. 7.6.3  INTERRUPT MASK Register
      4. 7.6.4  POWER EVENT Register
      5. 7.6.5  DETECTION EVENT Register
      6. 7.6.6  FAULT EVENT Register
      7. 7.6.7  START/ILIM EVENT Register
      8. 7.6.8  SUPPLY EVENT Register
      9. 7.6.9  PORT 1 STATUS Register
      10. 7.6.10 PORT 2 STATUS Register
      11. 7.6.11 PORT 3 STATUS Register
      12. 7.6.12 PORT 4 STATUS Register
      13. 7.6.13 POWER STATUS Register
      14. 7.6.14 Pin Status Register
      15. 7.6.15 OPERATING MODE Register
      16. 7.6.16 DISCONNECT ENABLE Register
      17. 7.6.17 DETECT/CLASS ENABLE Register
      18. 7.6.18 Port Power Priority/ICUT Disable Register Name
      19. 7.6.19 TIMING CONFIGURATION Register
      20. 7.6.20 GENERAL MASK Register
      21. 7.6.21 DETECT/CLASS RESTART Register
      22. 7.6.22 POWER ENABLE Register
      23. 7.6.23 RESET Register
      24. 7.6.24 ID Register
      25. 7.6.25 Police 21 Configuration Register
      26. 7.6.26 Police 43 Configuration Register
      27. 7.6.27 IEEE Power Enable Register
      28. 7.6.28 Power-on Fault Register
      29. 7.6.29 PORT RE-MAPPING Register
      30. 7.6.30 Port 21 Multi Bit Priority Register
      31. 7.6.31 Port 43 Multi Bit Priority Register
      32. 7.6.32 TEMPERATURE Register
      33. 7.6.33 INPUT VOLTAGE Register
      34. 7.6.34 PORT 1 CURRENT Register
      35. 7.6.35 PORT 2 CURRENT Register
      36. 7.6.36 PORT 3 CURRENT Register
      37. 7.6.37 PORT 4 CURRENT Register
      38. 7.6.38 PORT 1 VOLTAGE Register
      39. 7.6.39 PORT 2 VOLTAGE Register
      40. 7.6.40 PORT 3 VOLTAGE Register
      41. 7.6.41 PORT 4 VOLTAGE Register
      42. 7.6.42 PoE Plus Register
      43. 7.6.43 FIRMWARE REVISION
      44. 7.6.44 I2C WATCHDOG Register
      45. 7.6.45 DEVICE ID Register
      46. 7.6.46 PORT 1 DETECT RESISTANCE Register
      47. 7.6.47 PORT 2 DETECT RESISTANCE Register
      48. 7.6.48 PORT 3 DETECT RESISTANCE Register
      49. 7.6.49 PORT 4 DETECT RESISTANCE Register
  9. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Introduction to PoE
      2. 8.1.2 TPS2388 Application
      3. 8.1.3 Kelvin Current Sensing Resistor
      4. 8.1.4 Connections on Unused Ports
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Power Pin Bypass Capacitors
        2. 8.2.2.2 Per Port Components
        3. 8.2.2.3 System Level Components (not shown in the schematic diagrams)
      3. 8.2.3 Application Curves
    3. 8.3 Power Supply Recommendations
      1. 8.3.1 VDD
      2. 8.3.2 VPWR
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
        1. 8.4.1.1 Port Current Kelvin Sensing
      2. 8.4.2 Layout Example
        1. 8.4.2.1 Component Placement and Routing Guidelines
          1. 8.4.2.1.1 Power Pin Bypass Capacitors
          2. 8.4.2.1.2 Per-Port Components
  10. 9 Device and Documentation Support
    1. 9.1 Receiving Notification of Documentation Updates
    2. 9.2 Support Resources
    3. 9.3 Trademarks
    4. 9.4 Electrostatic Discharge Caution
    5. 9.5 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

5.6 Timing Requirements

MINTYPMAXUNIT
fSCLSCL clock frequency10400kHz
tLOWLOW period of the clock1.3µs
tHIGHHIGH period of the clock0.6µs
tfoSDAO output fall timeSDAO, 2.3 → 0.8V, Cb = 10pF,
10kΩ pull-up to 3.3V		21250ns
SDAO, 2.3 → 0.8V, Cb = 400pF,
1.3kΩ pull-up to 3.3V		21250ns
CI2CSCL capacitance10pF
CI2C_SDASDAI, SDAO capacitance (each)6pF
tSU,DATWData set-up time (Write operation)100ns
tSU,DATRData set-up time (Read operation)SDAO, Cb = 10pF,
1.3kΩ pull-up to 3.3V		600ns
tHD,DATWData hold time (Write operation)0ns
tHD,DATRData hold time (Read operation)150600ns
tfSDAInput fall times of SDAI2.3 → 0.8V20250ns
trSDAInput rise times of SDAI0.8 → 2.3V20300ns
trInput rise time of SCL0.8 → 2.3V20300ns
tfInput fall time of SCL2.3 → 0.8V20200ns
tBUFBus free time between a STOP and START condition1.3µs
tHD,STAHold time after (repeated) Start condition0.6µs
tSU,STARepeated Start condition set-up time0.6µs
tSU,STOStop condition set-up time0.6µs
tFLT_INTFault to INT assertionTime to internally register an Interrupt fault, from port turn off50500µs
tDGSuppressed spike pulse width, SDAI and SCL50ns
tRDGRESET input minimum pulse width (deglitch time)5µs
tbit_OSS3-bit OSS bit periodMbitPrty = 1242526µs
tOSS_IDLIdle time between consecutive shutdown code transmission in 3-bit modeMbitPrty = 14850µs
tr_OSSInput rise time of OSS in 3-bit mode0.8 → 2.3V, MbitPrty = 11300ns
tf_OSSInput fall time of OSS in 3-bit mode2.3 → 0.8V, MbitPrty = 11300ns
tWDT_I2CI2C Watchdog trip delay1.12.23.3s