SLUSC25B February   2015  – October 2026 TPS2388

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
    1. 4.1 Detailed Pin Description
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Timing Requirements
    7. 5.7 Switching Characteristics
    8. 5.8 Typical Characteristics
  7. 6 Parameter Measurement Information
    1. 6.1 Timing Diagrams
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Port Remapping
      2. 7.3.2 Port Power Priority
      3. 7.3.3 A/D Converter
      4. 7.3.4 I2C Watchdog
      5. 7.3.5 Foldback Protection
    4. 7.4 Device Functional Modes
      1. 7.4.1 Port Operating Modes
        1. 7.4.1.1 Semiauto
        2. 7.4.1.2 Manual
        3. 7.4.1.3 Power Off
      2. 7.4.2 Detection
      3. 7.4.3 Classification
      4. 7.4.4 DC Disconnect
    5. 7.5 Programming
      1. 7.5.1 I2C Serial Interface
    6. 7.6 Register Maps
      1. 7.6.1  Complete Register Set
      2. 7.6.2  INTERRUPT Register
      3. 7.6.3  INTERRUPT MASK Register
      4. 7.6.4  POWER EVENT Register
      5. 7.6.5  DETECTION EVENT Register
      6. 7.6.6  FAULT EVENT Register
      7. 7.6.7  START/ILIM EVENT Register
      8. 7.6.8  SUPPLY EVENT Register
      9. 7.6.9  PORT 1 STATUS Register
      10. 7.6.10 PORT 2 STATUS Register
      11. 7.6.11 PORT 3 STATUS Register
      12. 7.6.12 PORT 4 STATUS Register
      13. 7.6.13 POWER STATUS Register
      14. 7.6.14 Pin Status Register
      15. 7.6.15 OPERATING MODE Register
      16. 7.6.16 DISCONNECT ENABLE Register
      17. 7.6.17 DETECT/CLASS ENABLE Register
      18. 7.6.18 Port Power Priority/ICUT Disable Register Name
      19. 7.6.19 TIMING CONFIGURATION Register
      20. 7.6.20 GENERAL MASK Register
      21. 7.6.21 DETECT/CLASS RESTART Register
      22. 7.6.22 POWER ENABLE Register
      23. 7.6.23 RESET Register
      24. 7.6.24 ID Register
      25. 7.6.25 Police 21 Configuration Register
      26. 7.6.26 Police 43 Configuration Register
      27. 7.6.27 IEEE Power Enable Register
      28. 7.6.28 Power-on Fault Register
      29. 7.6.29 PORT RE-MAPPING Register
      30. 7.6.30 Port 21 Multi Bit Priority Register
      31. 7.6.31 Port 43 Multi Bit Priority Register
      32. 7.6.32 TEMPERATURE Register
      33. 7.6.33 INPUT VOLTAGE Register
      34. 7.6.34 PORT 1 CURRENT Register
      35. 7.6.35 PORT 2 CURRENT Register
      36. 7.6.36 PORT 3 CURRENT Register
      37. 7.6.37 PORT 4 CURRENT Register
      38. 7.6.38 PORT 1 VOLTAGE Register
      39. 7.6.39 PORT 2 VOLTAGE Register
      40. 7.6.40 PORT 3 VOLTAGE Register
      41. 7.6.41 PORT 4 VOLTAGE Register
      42. 7.6.42 PoE Plus Register
      43. 7.6.43 FIRMWARE REVISION
      44. 7.6.44 I2C WATCHDOG Register
      45. 7.6.45 DEVICE ID Register
      46. 7.6.46 PORT 1 DETECT RESISTANCE Register
      47. 7.6.47 PORT 2 DETECT RESISTANCE Register
      48. 7.6.48 PORT 3 DETECT RESISTANCE Register
      49. 7.6.49 PORT 4 DETECT RESISTANCE Register
  9. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Introduction to PoE
      2. 8.1.2 TPS2388 Application
      3. 8.1.3 Kelvin Current Sensing Resistor
      4. 8.1.4 Connections on Unused Ports
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Power Pin Bypass Capacitors
        2. 8.2.2.2 Per Port Components
        3. 8.2.2.3 System Level Components (not shown in the schematic diagrams)
      3. 8.2.3 Application Curves
    3. 8.3 Power Supply Recommendations
      1. 8.3.1 VDD
      2. 8.3.2 VPWR
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
        1. 8.4.1.1 Port Current Kelvin Sensing
      2. 8.4.2 Layout Example
        1. 8.4.2.1 Component Placement and Routing Guidelines
          1. 8.4.2.1.1 Power Pin Bypass Capacitors
          2. 8.4.2.1.2 Per-Port Components
  10. 9 Device and Documentation Support
    1. 9.1 Receiving Notification of Documentation Updates
    2. 9.2 Support Resources
    3. 9.3 Trademarks
    4. 9.4 Electrostatic Discharge Caution
    5. 9.5 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

7.6.19 TIMING CONFIGURATION Register

COMMAND = 16h with 1 Data Byte, Read/Write

Bit Descriptions: These bits define the timing configuration for all four ports.

Note: the PGn and PEn bits (Power Status register) are cleared when there is a TLIM, TOVLD, TMPDO, or TSTART fault condition.

Figure 7-23 TIMING CONFIGURATION Register Format
76543210
TLIMTSTARTTOVLDTMPDO
R/W-0R/W-0R/W-0R/W-0R/W-0R/W-0R/W-0R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 7-18 TIMING CONFIGURATION Register Field Descriptions
BitFieldTypeResetDescription
7 –6TLIMR/W0ILIM fault timing, which is the output current limit time duration before port turn off.

This timer is active and increments to the settings defined below after expiration of the TSTART time window and when the port is limiting its output current to ILIM. If the ILIM counter is allowed to reach the programmed time-out duration specified below, the port will be powered off. The 1-second cool down timer is then started, and the port can not be turned-on until the counter has reached completion.

In other circumstances (ILIM time-out has not been reached), while the port current is below ILIM, the same counter decrements at a rate 1/16th of the increment rate. The counter does not decrement below zero. The ILIM counter is also cleared in the event of a port turn off due to a Power Enable or Port Reset command, a DC disconnect event or the OSS input.

Note that in the event the TLIM setting is changed while this timer is already active for a port, this timer is automatically reset then restarted with the new programmed time-out duration.

Note that at the end of cool down cycle, when in semiauto mode, a detection cycle is automatically restarted if the detect enable bit is set. Also note that the cool down time count is immediately canceled with a port reset command, or if the OFF or Manual mode is selected.

When a PoEPn bit in PoE Plus register is deasserted, the tLIM used for the associated port is always the nominal value (about 60ms).

If PoEPn bit is asserted, then tLIM for associated port is programmable with the following selection:

TLIMNominal tLIM (ms)
0060
0115
1012
1110
5-4TSTART

(or TINRUSH)

R/W0START fault timing, which is the maximum allowed overcurrent time during inrush. If at the end of TSTART period the current is still limited to IInrush, the port is powered off.

This is followed by a 1-second cool down period, during which the port can not be turned-on

Note that at the end of cool down cycle, when in semiauto mode, a detection cycle is automatically restarted if the class and detect enable bits are set.

Note that in the event the TSTART setting is changed while this timer is already active for a port, this new setting is ignored and will be applied only next time the port is turned ON.

The selection is as following:

TSTARTNominal tSTART (ms)
0060
0130
10120
11Reserved
3–2TOVLDR/W0ICUT fault timing, which is the overcurrent time duration before port turn off. This timer is active and increments to the settings defined below after expiration of the TSTART time window and when the port current meets or exceeds ICUT, or when it is limited by the current foldback. If the ICUT counter is allowed to reach the programmed time-out duration specified below, the port will be powered off. The 1-second cool down timer is then started, and the port can not be turned-on until the counter has reached completion.

In other circumstances (ICUT time-out has not been reached), while the port current is below ICUT, the same counter decrements at a rate 1/16th of the increment rate. The counter does not decrement below zero. The ICUT counter is also cleared in the event of a port turn off due to a Power Enable or Port Reset command, a DC disconnect event or the OSS input

Note that in the event the TOVLD setting is changed while this timer is already active for a port, this timer is automatically reset then restarted with the new programmed time-out duration.

Note that at the end of cool down cycle, when in semiauto mode, a detection cycle is automatically restarted if the detect enable bit is set. Also note that the cool down time count is immediately canceled with a port reset command, or if the OFF or Manual mode is selected.

Note that if a DCUTn bit is high in the Port Power Priority/ICUT Disable register, the ICUT fault timing for the associated port is disabled. This means that this port will not be turned off if there is only ICUT fault.

The selection is as following:

TOVLDNominal tOVLD (ms)
0060
0130
10120
11240
1–0TMPDOR/W0Disconnect delay, which is the time to turn off a port once there is a disconnect condition, and if the dc disconnect detect method has been enabled.

The TDIS counter is reset each time the current goes continuously higher than the disconnect threshold for nominally 15ms.

The counter does not decrement below zero.

The selection is as following:

TMPDONominal tMPDO (ms)
00360
0190
10180
11720