SLUSC82B April   2017  – July 2026 UCC24630

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Timing Requirements
    7. 5.7 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 Start Up and UVLO
      2. 6.3.2 Volt-Sec SR Driver On-Time Control
      3. 6.3.3 CCM Dead Time
      4. 6.3.4 Standby Operation
      5. 6.3.5 Pin Fault Protection
        1. 6.3.5.1 VPC Pin Overvoltage
        2. 6.3.5.2 VPC Pin Open
        3. 6.3.5.3 VSC Pin Open
        4. 6.3.5.4 TBLK Pin Open
        5. 6.3.5.5 VPC and VSC Short to Ground
        6. 6.3.5.6 TBLK Pin Short to Ground
    4. 6.4 Device Functional Modes
      1. 6.4.1 Start-Up
      2. 6.4.2 Normal Operation
      3. 6.4.3 Standby Operation
      4. 6.4.4 Conditions to Stop Operation
  8. 7 Application and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Application
      1. 7.2.1 AC-to-DC Adapter, 19.5V, 65W
      2. 7.2.2 Design Requirements
      3. 7.2.3 Calculation of Component Values
        1. 7.2.3.1 VPC Input
        2. 7.2.3.2 VSC Input
        3. 7.2.3.3 TBLK Input
      4. 7.2.4 Application Curves
    3. 7.3 Best Design Practices
    4. 7.4 Power Supply Recommendations
    5. 7.5 Layout
      1. 7.5.1 Layout Guidelines
        1. 7.5.1.1 VDD Pin
        2. 7.5.1.2 VPC Pin
        3. 7.5.1.3 VSC Pin
        4. 7.5.1.4 GND Pin
        5. 7.5.1.5 TBLK Pin
        6. 7.5.1.6 DRV Pin
      2. 7.5.2 Layout Example
  9. 8 Device and Documentation Support
    1. 8.1 Device Support
      1. 8.1.1 Device Nomenclature
        1. 8.1.1.1 Definition of Terms
    2. 8.2 Receiving Notification of Documentation Updates
    3. 8.3 Support Resources
    4. 8.4 Trademarks
    5. 8.5 Electrostatic Discharge Caution
    6. 8.6 Glossary
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information

6.3.1 Start Up and UVLO

The UCC24630 features a wide operating VDD range and low UVLO thresholds. The start up of the device depends on voltage levels on three pins: VDD, VPC and VSC. The VDD pin can be directly connected to the power supply output on converters from 5V to 24V nominal outputs. The start UVLO threshold is VVDD(on), 4.0V typical, and stop threshold is VVDD(off), 3.6V typical. The DRV output is not enabled unless the voltage on the VPC pin is greater than VVPCEN for a time longer than tVPC-BLK and the voltage on the VSC pin is greater than VVSCEN. Once the VDD, VSC and VPC voltage and time thresholds are met, there is an internal initialization time and a four-cycle-initialization start sequence before the DRV output is enabled.

See Figure 6-1 for a startup sequence that shows the timing sequence and configurable DRV output based on VDD level. In most converter designs, the conditions for the VPC and VSC voltage to enable the device are met before the VDD start-voltage threshold, this is reflected in the timing diagram. When VDD exceeds VVDD(on) UVLO threshold the device starts the initialization sequence from 150µs to 250µs illustrated as tINITIALIZE. After the device initialization, there is a logic initialization of 20µs at which time VTBLK is enabled (high). After the device is enabled, the CCM dead-time block requires four cycles to initialize the dead-time control before the DRV output is enabled. At VDD < VPMOS the driver high-side PMOS device is enabled and the DRV peak is close to VDD. When VDD exceeds VPMOS the PMOS device is disabled and the driver is operating as a high-side NMOS only and DRV is approximately from 1.2V to 1.5V lower than VDD. As VDD continues to increase, the DRV output is limited to VDRCL regardless of VDD up to the recommended maximum rating.

UCC24630 Start-Up OperationFigure 6-1 Start-Up Operation