SLUSC82B April   2017  – July 2026 UCC24630

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Timing Requirements
    7. 5.7 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 Start Up and UVLO
      2. 6.3.2 Volt-Sec SR Driver On-Time Control
      3. 6.3.3 CCM Dead Time
      4. 6.3.4 Standby Operation
      5. 6.3.5 Pin Fault Protection
        1. 6.3.5.1 VPC Pin Overvoltage
        2. 6.3.5.2 VPC Pin Open
        3. 6.3.5.3 VSC Pin Open
        4. 6.3.5.4 TBLK Pin Open
        5. 6.3.5.5 VPC and VSC Short to Ground
        6. 6.3.5.6 TBLK Pin Short to Ground
    4. 6.4 Device Functional Modes
      1. 6.4.1 Start-Up
      2. 6.4.2 Normal Operation
      3. 6.4.3 Standby Operation
      4. 6.4.4 Conditions to Stop Operation
  8. 7 Application and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Application
      1. 7.2.1 AC-to-DC Adapter, 19.5V, 65W
      2. 7.2.2 Design Requirements
      3. 7.2.3 Calculation of Component Values
        1. 7.2.3.1 VPC Input
        2. 7.2.3.2 VSC Input
        3. 7.2.3.3 TBLK Input
      4. 7.2.4 Application Curves
    3. 7.3 Best Design Practices
    4. 7.4 Power Supply Recommendations
    5. 7.5 Layout
      1. 7.5.1 Layout Guidelines
        1. 7.5.1.1 VDD Pin
        2. 7.5.1.2 VPC Pin
        3. 7.5.1.3 VSC Pin
        4. 7.5.1.4 GND Pin
        5. 7.5.1.5 TBLK Pin
        6. 7.5.1.6 DRV Pin
      2. 7.5.2 Layout Example
  9. 8 Device and Documentation Support
    1. 8.1 Device Support
      1. 8.1.1 Device Nomenclature
        1. 8.1.1.1 Definition of Terms
    2. 8.2 Receiving Notification of Documentation Updates
    3. 8.3 Support Resources
    4. 8.4 Trademarks
    5. 8.5 Electrostatic Discharge Caution
    6. 8.6 Glossary
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information

6.3.2 Volt-Sec SR Driver On-Time Control

See the timing diagrams in Figure 6-2 and Figure 6-3 for functional details of the UCC24630 volt-sec on-time control.

UCC24630 Operation in DCM Figure 6-2 Operation in DCM
UCC24630 Operation in CCM Figure 6-3 Operation in CCM

The UCC24630 uses the VPC and VSC pins to sense the SR MOSFET VDS voltage and converter VOUT voltage through resistor dividers. The information of VIN/NPS, tPRI, and VOUT is obtainable from the information on VPC and VSC pins. The SR MOSFET turn-on is determined when the SR MOSFET body diode starts conducting and the VPC pin voltage falls to near zero; the SR MOSFET turn-off is determined by the current emulator control ramps. The SR timing determined by the volt-sec balance function is the dominant mode of operation with all flyback converters, including CCM.

The UCC24630 volt-sec control generates the internal VPC ramp and VSC ramp to emulate the transformer Volt-Sec balancing as shown in Figure 6-2 and Figure 6-3.

The secondary current discharge time, tSEC-DIS is indirectly determined. The primary volt-sec ramp and secondary volt-sec ramp both start when VPC rises above VVPCEN and VVPC-TH. The charge currents for the VPC and VSC ramps are determined by the voltage on the VPC and VSC pins respectively.

When VPC is higher than VVPCEN and VVPC-TH for t > tVPC-BLK, the VPC pulse is qualified as a primary conduction pulse and the SR is enabled on the VPC falling edge. The VPC ramp continues to rise until the VPC falling edge based on the real-time voltage on the VPC pin and holds the peak for the cycle. The DRV output is turned on during the VPC falling edge near zero volts, and DRV is turned off when the VSC rising ramp crosses the VPC ramp held level.

Both VPC and VSC ramps are reset to zero on each VPC rising edge above the VVPCEN and VVPC-TH thresholds.

To discriminate primary on-time pulses from DCM ringing, there are voltage and time criteria that must be satisfied on the VPC pin to enable the DRV output. tVPC-BLK can be adjusted through the resistor on TBLK pin.

At the rising edge of VPC when the voltage exceeds VVPCEN and VVPC-TH the blanking time tVPC-BLK is initiated. At the end of tVPC-BLK, the VPC voltage is sampled during tVPC-SPL window, which is 100ns nominal. Also at the end of tVPC-BLK, the DRV output is enabled.

The VPC voltage sampled during tVPC-SPL determines the VPC dynamic threshold VVPC-TH which is normally 85% of the sampled VPC voltage. The dynamic threshold provides the ability to reject the DCM ringing and detect the primary on-time. Noise immunity during the turn-on event of DRV at the falling edge of the VPC pin is enhanced by a minimum DRV on time of tSRONMIN, which is 350ns nominal.

During the falling edge of DRV, the tOFF timer is initiated which inhibits turn-on of the SR until tOFF expires. This eliminates false turn-on of DRV if the DCM ringing is close to ground.

The UCC24630 is designed to operate in a variety of flyback converter applications over a wide operating range. The internal volt-sec control ramps do have a dynamic range limit based on volt-sec on the VPC pin. As shown in Figure 6-4, a Volt-sec product exceeding 7V-µs on the VPC pin results in saturation of the VPC volt-sec control ramp. Operation beyond this point results in a DRV on-time less than expected. For example, if VVPC = 0.5V, tVPC must be < 14µs, or if VVPC = 2.0V, tVPC must be < 3.5µs, to operate within the dynamic range of the device. Assuming a converter operating in transition mode at low line and full load with a 50% duty cycle, the operating period is 28µs which results in a frequency that is under 40kHz. The UCC24630 low-frequency operating range extends to the standby mode threshold of 5kHz; but each switching cycle VVPC Volt-sec product must be less than 7V-µs.

The device can support switching frequencies exceeding 200kHz but the following timing limits need to be confirmed to be compatible with the power train. The minimum primary on time when the device is expected to be active must be compatible with the minimum VPC blanking time (tVPC-BLK) setting of 203ns plus the sampling window (tVPC-SPL) of 100ns. The minimum secondary current conduction time must be larger than the minimum SR on time (tSR(min)) of 350ns. The minimum time from the SR drive turn-off until the next SR drive turn-on must be greater than the SR minimum off time (tOFF) of 2.5µs.

UCC24630 RatioVPC_VSC vs VPC V-µs Figure 6-4 RatioVPC_VSC vs VPC V-µs
UCC24630 SR Controller Components Figure 6-5 SR Controller Components

Determining the VPC and VSC divider resistors is based on the operating voltage ranges of the converter and RatioVPC-VSC gain ratio. Referring to Figure 6-5, the following equation determines the VPC divider values.

For R2a value of 10kΩ is recommended for minimal impact on time delay, and low-resistor dissipation. A higher R2 value reduces resistor divider dissipation but can increase the DRV turn-on delay due to the time constant of ~2pF pin capacitance and divider resistance. A lower R2 value can be used with the trade-off of higher dissipation in the resistor divider. A factor of 10% over the VPC threshold, VVPCEN, is shown in Equation 1 for design margin.

Equation 1. R 1 = ( [ V I N ( m i n ) N P S + V O U T ( m i n ) ] - V V P C E N × 1.1 ) × R 2 V V P C E N × 1.1

where

  • VIN(min) is the converter minimum primary bulk capacitor voltage.
  • VOUT(min) is the minimum converter output voltage in normal operation.
  • VVPCEN is the VPC enable threshold, use the specified maximum value.
  • NPS is the transformer primary to secondary turns ratio.

The operating voltage range on the VPC pin must be within the range of 0.45V < VVPC < 2V. Referring to Figure 5-6, if VVPC is greater than 2.3V the dynamic range is exceeded and RatioVPC_VSC is reduced; in this condition the DRV on time is less than expected. If VVPC is greater than 2.6V for 500ns, a fault is generated and DRV is disabled for the cycle, see Section 6.3.5. To establish the maximum voltage is within range confirm with Equation 2.

Equation 2. V V P C ( m a x ) = [ V I N ( m a x ) N P S + V O U T ( m a x ) ] × R 2 R 1 + R 2

where

  • VIN(max) is the converter maximum primary bulk capacitor voltage.
  • VOUT(max) is the maximum converter output voltage at OVP.
  • NPS is the transformer primary-to-secondary turns ratio.

The program voltage on the VSC pin is determined by the VPC divider ratio and the device's parameter RatioVPC_VSC. The current emulator ramp gain is higher on the VPC pin by the multiple RatioVPC_VSC, so the VSC resistor divider ratio is reduced by the same RatioVPC_VSC accordingly. Determine the VSC divider resistors using equation 3 below. To minimize resistor divider dissipation, a recommended range for R4 is from 25kΩ to 50kΩ. Higher R4 values results in increasing offset due to VSC input current, IVSC. Lower R4 values increases the resistor divider dissipation. To establish DRV turn off slightly before the secondary current reaches zero, 10% margin is shown for initial values. Use a nominal value of 4.15 for RatioVPC_VSC.

Equation 3. R 3 = [ ( R 1 + R 2 R 2 R a t i o V P C _ V S C × 1.1 ) - 1 ] × R 4

where

  • RatioVPC_VSC is the device parameter VPC and VSC gain ratio, use a value of 4.15.

The operating voltage on the VSC pin must be within the range of 0.3V < VVSC < 2V. Referring to Figure 5-7, if VVSC is greater than 2.3V, the dynamic range is exceeded and RatioVPC_VSC is increased; in this condition the DRV on time is more than expected. To establish the VSC voltage is within range confirm with Equation 4 and Equation 5.

Equation 4. R 4 R 3 + R 4 × V O U T ( m i n ) ≥ 0.3 V
Equation 5. R 4 R 3 + R 4 × V O U T ( m i n ) ≤ 2.0 V

where

  • VOUT(min) is the minimum converter output operating voltage of the SR controller.
  • VOUT(max) is the maximum converter output operating voltage of the voltage at OVP.

Discrimination of ringing during DCM operation from valid primary on-time is achieved by a dynamic VPC rising threshold and programmable blanking time. The dynamic threshold VVPC-TH is 85% typical ratio of the previous VPC pin peak voltage. Referring to Figure 6-2, the VPC pin voltage is sampled after the VPC voltage is greater than VVPCEN and VVPC-TH for t > tVPC-BLK. The function of the dynamic threshold VVPC-TH is to reject the ringing in DCM operation from the primary conduction pulses. The dynamic threshold has an active range from the minimum VVPCEN voltage to a maximum of 1V clamp. The blanking time is programmable from 200ns to 1µs to accommodate a variety of converter designs.

See Figure 6-6 for guidance on selecting the blanking time. The blanking time must be selected as long as reasonable and still accommodate the minimum primary on-time at light-load condition and high-line voltage. In the high-line minimum load condition, select a blanking time that meets the following criteria (Equation 6) to accommodate tolerance of the blanking time and the tVPC-SPL sampling time window.

Equation 6. t V P C - B L K = ( t P R I × 0.85 ) - 120 n s

For rejection of DCM ringing, the blanking time must be longer than the time that the ring is above the VVPC-TH dynamic threshold, which is 85% of the minimum SR VDS peak voltage. Determine these criteria at low line and maximum load condition. It is recommended that the transformer turns ratio be selected such that the secondary reflected voltage is < 85% of VIN(min) bulk capacitor voltage at the highest load when DCM operation occurs at the low line input condition.

To determine the resistor value for tVPC-BLK use Equation 7 to select from a range from 200ns to 1µs.

Equation 7. R 5 = t V P C - B L K - 100 n s 18 p F

where

  • tVPC-BLK is the target blanking time.

Additional discrimination for proper SR timing control is provided by the tOFF function. See Figure 6-2 and Figure 6-3 for the timing details. After the DRV turn-off, the DRV is inhibited from turning on again until the tOFF timer expires. This protects against SR false turn-on from SR VDS DCM ringing below ground.

UCC24630 VPC Blanking Time Criteria Figure 6-6 VPC Blanking Time Criteria