SLUSFX8 September   2026 UCC218302-Q1

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Power Ratings
    6. 5.6 Insulation Specifications
    7. 5.7 Electrical Characteristics
    8. 5.8 Switching Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1  Power Supply
      2. 6.3.2  VCC Undervoltage Lockout (UVLO)
      3. 6.3.3  Input Filters for IN+, IN-, and RST/EN
      4. 6.3.4  Active Pulldown
      5. 6.3.5  Short Circuit Clamping
      6. 6.3.6  Internal Active Miller Clamp
      7. 6.3.7  Desaturation (DESAT) Protection
      8. 6.3.8  Soft Shutdown (SSD)
      9. 6.3.9  Fault (FLT), Reset, and Enable (RST/EN)
      10. 6.3.10 Output Gate Voltage Monitor
      11. 6.3.11 Active Short Circuit (ASC) Support
      12. 6.3.12 Overtemperature Protection
    4. 6.4 Device Functional Modes
  8. 7 Applications and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Application
      1. 7.2.1 Application Schematic
      2. 7.2.2 Design Requirements
      3. 7.2.3 Detailed Design Procedure
        1. 7.2.3.1 Input Filters for IN+, IN-, and RST/EN
        2. 7.2.3.2 FLT, RDY, and RST/EN Pin Circuitry
        3. 7.2.3.3 Gate Driver Output Resistors
        4. 7.2.3.4 Overcurrent and Short Circuit Protection With DESAT
      4. 7.2.4 Application Curves
    3. 7.3 Power Supply Recommendations
    4. 7.4 Layout
      1. 7.4.1 Layout Guidelines
      2. 7.4.2 Layout Example
  9. 8 Device and Documentation Support
    1. 8.1 Third-Party Products Disclaimer
    2. 8.2 Documentation Support
      1. 8.2.1 Related Documentation
    3. 8.3 Receiving Notification of Documentation Updates
    4. 8.4 Support Resources
    5. 8.5 Trademarks
    6. 8.6 Electrostatic Discharge Caution
    7. 8.7 Glossary
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information
    1. 10.1 Mechanical Data

6.3.9 Fault (FLT), Reset, and Enable (RST/EN)

The FLT pin is open drain and can report a fault signal to the DSP/MCU when the DESAT pin detects a fault. The FLT pin pulls down to GND after detecting a fault, and is held low until receiving a reset signal from RST/EN. The device has a fault mute time tFLTMUTE, within which the device ignores any reset signal.

The RST/EN pin is pulled down internally and is thus disabled by default when this pin is floating. The pin must be pulled up externally to enable the driver. The pin has two purposes:

  • To enable and shut down the device. If the RST/EN pin pulls low for longer than tINFIL, the driver disables and depending on GD_SEL logic level, OUTLx activates to turn off the gate of the IGBT or SiC MOSFET.
  • To reset the DESAT fault signaled on the FLT pin. If the RST/EN pin pulls low for more than tRSTFIL after the mute time tFLTMUTE, then the fault signal is reset and FLT returns to a high-impedance state upon the next rising edge applied to the RST/EN pin. Figure 6-10 shows a timing diagram.