SLUSFX8 September   2026 UCC218302-Q1

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Power Ratings
    6. 5.6 Insulation Specifications
    7. 5.7 Electrical Characteristics
    8. 5.8 Switching Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1  Power Supply
      2. 6.3.2  VCC Undervoltage Lockout (UVLO)
      3. 6.3.3  Input Filters for IN+, IN-, and RST/EN
      4. 6.3.4  Active Pulldown
      5. 6.3.5  Short Circuit Clamping
      6. 6.3.6  Internal Active Miller Clamp
      7. 6.3.7  Desaturation (DESAT) Protection
      8. 6.3.8  Soft Shutdown (SSD)
      9. 6.3.9  Fault (FLT), Reset, and Enable (RST/EN)
      10. 6.3.10 Output Gate Voltage Monitor
      11. 6.3.11 Active Short Circuit (ASC) Support
      12. 6.3.12 Overtemperature Protection
    4. 6.4 Device Functional Modes
  8. 7 Applications and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Application
      1. 7.2.1 Application Schematic
      2. 7.2.2 Design Requirements
      3. 7.2.3 Detailed Design Procedure
        1. 7.2.3.1 Input Filters for IN+, IN-, and RST/EN
        2. 7.2.3.2 FLT, RDY, and RST/EN Pin Circuitry
        3. 7.2.3.3 Gate Driver Output Resistors
        4. 7.2.3.4 Overcurrent and Short Circuit Protection With DESAT
      4. 7.2.4 Application Curves
    3. 7.3 Power Supply Recommendations
    4. 7.4 Layout
      1. 7.4.1 Layout Guidelines
      2. 7.4.2 Layout Example
  9. 8 Device and Documentation Support
    1. 8.1 Third-Party Products Disclaimer
    2. 8.2 Documentation Support
      1. 8.2.1 Related Documentation
    3. 8.3 Receiving Notification of Documentation Updates
    4. 8.4 Support Resources
    5. 8.5 Trademarks
    6. 8.6 Electrostatic Discharge Caution
    7. 8.7 Glossary
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information
    1. 10.1 Mechanical Data

7.2.3.3 Gate Driver Output Resistors

The device features dual split outputs OUTH1, OUTH2, OUTL1 and OUTL2, which enables the independent control of the turn-on and turn-off switching speeds. The turn-on and turn-off resistances determine the peak source and sink current, which control the switching speed. Meanwhile, consider the power dissipation in the gate driver to establish the device is in the thermal limit. OUTH1 and OUTL1 can source and sink ±5A peak current. OUTH2 and OUTL2 can source and sink ±10A peak current. At first, calculate the peak source and sink current as:

Equation 1. I S o u r c e _ P k _ O U T H 1 =   m i n 5 A ,   V D D -   V E E ∕ R O U T H 1 + R O N 1 + R G _ I n t
Equation 2. I S i n k _ P k _ O U T L 1 =   m i n 5 A ,   V D D -   V E E ∕ R O U T L 1 + R O F F 1 + R G _ I n t
Equation 3. I S i n k _ P k _ O U T H 2 =   m i n 10 A ,   V D D -   V E E ∕ R O U T H 2 + R O N 2 + R G _ I n t
Equation 4. I S i n k _ P k _ O U T L 2 =   m i n 10 A ,   V D D -   V E E ∕ R O U T L 2 + R O F F 2 + R G _ I n t

Where

  • ROUTH1 is the internal pullup resistance of OUTH1
  • ROUTH2 is the internal pullup resistance of OUTH2
  • ROUTL1 is the internal pulldown resistance of OUTL1
  • ROUTL2 is the internal pulldown resistance of OUTL2
  • RON1 is the external turn on gate resistance of OUTH1
  • RON2 is the external turn on gate resistance of OUTH2
  • ROFF1 is the external turn off gate resistance of OUTL1
  • ROFF2 is the external turn off gate resistance of OUTL2
  • RG_Int is the internal resistance of the SiC MOSFET or IGBT module
UCC218302-Q1 Output Model for Calculating Peak Gate Current Figure 7-5 Output Model for Calculating Peak Gate Current

The following example of calculation, uses the maximum values for the internal pullup and pulldown resistances. See also Electrical Characteristics for more information. For an IGBT module based system with the following parameters:

  • Qg = 3300nC
  • RG_Int = 1.7Ω
  • RON1 = ROFF1= 1.0Ω
  • RON2 = ROFF2= 0.5Ω
  • VDD = 15V
  • VEE = -5V

The peak source and sink current in this case are:

Equation 5. I S o u r c e _ P k _ OUTH1 = V D D - V E E / R O UTH1 +   R O N1 + R G _ I n t = 5A
Equation 6. I S i n k _ P k _ OUTL1 = V D D - V E E / R O UTL1 +   R O F F1 + R G _ I n t = 5A
Equation 7. I S o u r c e _ P k _ OUTH2 = V D D - V E E / R O UTH2 +   R O N2 + R G _ I n t = 6.7A
Equation 8. I S i n k _ P k _ OUTL2 = V D D - V E E / R O UTL2 +   R O F F2 + R G _ I n t = 6.7A

Using 1Ω external gate resistance, the peak source/sink current on OUT1 is 4A, the peak source/sink current on OUT2 is 6.7A. By setting the GD_SEL pin low or high, the device can provide a weak drive strength using only OUT1, or a strong drive strength using both OUT1 and OUT2. The weak and strong drive currents in this case are:

Equation 9. I S o u r c e _ P k _ Weak = I S o u r c e _ P k _ OUTH1 = 5A
Equation 10. I S i n k _ P k _ Weak = I S i n k _ P k _ OUTL1 = 5A
Equation 11. I S o u r c e _ P k _ Strong = I S o u r c e _ P k _ OUTH1 + I S o u r c e _ P k _ OUTH2 = 11.7A
Equation 12. I S i n k _ P k _ Strong = I S i n k _ P k _ OUTL1 + I S i n k _ P k _ OUTL2 = 11.7A

The gate current at the Miller plateau voltage dominates the collector-to-emitter dV/dt during the turn-on switching transient. The pullup structure verifies the peak source current at the Miller plateau voltage, unless the turn-on gate resistor is too high. The faster the collector-to-emitter, Vce, voltage rises to VDC, the smaller the turn-on switching loss. Estimate the dV/dt as Qgc/Isource_pk. For the turn-off switching transient, unless the turn-off gate resistor is too high, the load current dominates the drain-to-source dV/dt. After Vce reaches the DC bus voltage, the power semiconductor is in saturation mode and Vge controls the channel current. The peak sink current determines the dI/dt, which dominates the Vce voltage overshoot accordingly. If using relatively large turn-off gate resistance and weak drive selection, limit the Vce overshoot. Estimate the overshoot using:

Equation 13. Δ V c e = L s t r a y × I l o a d ∕ R O F F 1 + R O U T L 1 + R G _ I n t × C i e s × ln ⁡ V p l a t ∕ V t h

Where

  • Lstray is the stray inductance in power switching loop, as shown in Figure 7-6
  • Iload is the load current, which is the turn off current of the power semiconductor
  • Cies is the input capacitance of the power semiconductor
  • Vplat is the plateau voltage of the power semiconductor
  • Vth is the threshold voltage of the power semiconductor
UCC218302-Q1 Stray Parasitic Inductance of IGBTs in a Half-Bridge Configuration Figure 7-6 Stray Parasitic Inductance of IGBTs in a Half-Bridge Configuration

Take into account the power dissipation to maintain the gate driver within the thermal limit. Calculate the power loss of the gate driver includes the quiescent loss and the switching loss as:

Equation 14. P D R = P Q + P S W

PQ is the quiescent power loss for the driver, which is Iq × (VDD-VEE) = 7mA × 20V = 0.14W. The quiescent power loss is the power consumed by the internal circuits, such as the input stage, reference voltage, logic circuits, and protection circuits when the driver is switching, when the driver is biased with VDD and VEE, and the charging and discharging current of the internal circuit when the driver is switching. Considering that the strong drive strength is enabled, and for calculation simplicity, assuming the Qg flow distributes reverse proportionally to the total resistance on each output channel. Calculate the power dissipation of each output channel when the driver is switching as:

Equation 15. P S WOUTx1 = 1 2   × (   R OUT H1 R OUT H1 +   R O N1 + R G _ I n t +   R OUT L1 R OUT L1 +   R O F F1 + R G _ I n t ) ×   ( V D D - V E E ) ×   f s w × 1 3 × Q g  
Equation 16. P S WOUTx2 = 1 2   × (   R OUT H2 R OUT H1 +   R O N2 + R G _ I n t +   R OUT L2 R OUT L2 +   R O F F2 + R G _ I n t ) ×   ( V D D - V E E ) ×   f s w × 2 3 × Q g  

Where

  • Qg is the gate charge required at the operation point to fully charge the gate voltage from VEE to VDD
  • fsw is the switching frequency (30kHz)

In this example, by selecting the strong drive, calculate the PSW as:

Equation 17. P S W = P S WOUTx1 + P S WOUTx2 = 0.14 + 0.34 = 0.48 W  

Thus, the total power loss is:

Equation 18. P D R = P Q + P S W =   0.14 W + 0.56 W   =   0.70 W  

When the board temperature is 120°C, estimate the junction temperature as:

Equation 19. T j = T b + Ψ J B × P D R   ≈   150 ℃

Therefore, for the application in this example, with 120°C board temperature, the maximum switching frequency is approximately 30kHz to keep the gate driver in the thermal limit. By using a lower switching frequency or increasing external gate resistance, operate the gate driver at a higher board temperature.