SLUSFX8 September   2026 UCC218302-Q1

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Power Ratings
    6. 5.6 Insulation Specifications
    7. 5.7 Electrical Characteristics
    8. 5.8 Switching Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1  Power Supply
      2. 6.3.2  VCC Undervoltage Lockout (UVLO)
      3. 6.3.3  Input Filters for IN+, IN-, and RST/EN
      4. 6.3.4  Active Pulldown
      5. 6.3.5  Short Circuit Clamping
      6. 6.3.6  Internal Active Miller Clamp
      7. 6.3.7  Desaturation (DESAT) Protection
      8. 6.3.8  Soft Shutdown (SSD)
      9. 6.3.9  Fault (FLT), Reset, and Enable (RST/EN)
      10. 6.3.10 Output Gate Voltage Monitor
      11. 6.3.11 Active Short Circuit (ASC) Support
      12. 6.3.12 Overtemperature Protection
    4. 6.4 Device Functional Modes
  8. 7 Applications and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Application
      1. 7.2.1 Application Schematic
      2. 7.2.2 Design Requirements
      3. 7.2.3 Detailed Design Procedure
        1. 7.2.3.1 Input Filters for IN+, IN-, and RST/EN
        2. 7.2.3.2 FLT, RDY, and RST/EN Pin Circuitry
        3. 7.2.3.3 Gate Driver Output Resistors
        4. 7.2.3.4 Overcurrent and Short Circuit Protection With DESAT
      4. 7.2.4 Application Curves
    3. 7.3 Power Supply Recommendations
    4. 7.4 Layout
      1. 7.4.1 Layout Guidelines
      2. 7.4.2 Layout Example
  9. 8 Device and Documentation Support
    1. 8.1 Third-Party Products Disclaimer
    2. 8.2 Documentation Support
      1. 8.2.1 Related Documentation
    3. 8.3 Receiving Notification of Documentation Updates
    4. 8.4 Support Resources
    5. 8.5 Trademarks
    6. 8.6 Electrostatic Discharge Caution
    7. 8.7 Glossary
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information
    1. 10.1 Mechanical Data

5.7 Electrical Characteristics

VCC = 3.3V or 5.0V, 1µF capacitor from VCC to GND, VDD - COM = 20V, 18V or 15V, COM - VEE = 5V, 8V or 15V, CL = 100pF, -40°C < TJ < 150°C (unless otherwise noted)(1)(2).
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
POWER SUPPLY QUIESCENT CURRENT
IVCCQ VCC quiescent current OUT = Low, fs = 0Hz 3.5 5.6 mA
OUT = High, fs = 0Hz 6 8.4 mA
IVDDQ VDD quiescent current OUT = High, fs = 0Hz 7 8.1 mA
OUT = Low, fs = 0Hz 4 4.8 mA
IVEEQ VEE quiescent current OUT = High, fs = 0Hz, VEE = -5V -7.5 -6.4 mA
OUT = Low, fs = 0Hz, VEE = -5V -4.25 -3.7 mA
POWER SUPPLY PROTECTION
VVCC_ON VCC UVLO rising threshold Reference to GND 2.55 2.68 2.85 V
VVCC_OFF VCC UVLO falling threshold Reference to GND 2.35 2.51 2.65 V
VVCC_HYST VCC UVLO hysteresis 170 mV
tVCCFIL VCC UVLO deglitch time 3 µs
tVCC+ to OUT VCC UVLO on delay to output high IN+ = VCC, IN- = GND 7 16 µs
tVCC- to OUT VCC UVLO off delay to output low 6 9 µs
tVCC+ to RDY VCC UVLO on delay to RDY high RST/EN = VCC 8 16 µs
tVCC- to RDY VCC UVLO off delay to RDY low 7 10 µs
VVDD_UVLO_ON VDD UVLO rising threshold 11.4 12 12.6 V
VVDD_UVLO_OFF VDD UVLO falling threshold 10.45 11 11.55 V
VVDD_HYST VDD UVLO hysteresis 1 V
tVDDFIL VDD UVLO deglitch time 5 µs
tVDD+ to OUT VDD UVLO on delay to output high IN+ = VCC, IN- = GND 5 8 µs
tVDD- to OUT VDD UVLO off delay to output low 5 10 µs
tVDD+ to RDY VDD UVLO on delay to RDY high RST/EN = FLT = VCC 5 8 µs
tVDD- to RDY VDD UVLO off delay to RDY low 10 17 µs
PRIMARY SIDE LOGIC INPUTS (INx, RST/EN, GD_SEL)
VINH Logic-high input threshold voltage (% of VCC)   57 70 %
VINL Logic-low input threshold voltage (% of VCC) 30 42 %
VINHYS Input threshold hysteresis (% of VCC)   15   %
IIH Input high level input leakage current VIN = VCC 50 uA
IIL Input low level input leakage current VIN = GND   -50 uA
RIND Input pins pull down resistance IN+, RST/EN, GD_SEL 100 kΩ
RINU Input pins pull up resistance IN-, RDY, FLT 100 kΩ
tINFIL INx, and RST/EN deglitch (ON and OFF) filter time fS = 50kHz 16 25 50 ns
tRSTFIL Deglitch filter time to reset FLT   500 800 ns
tGDSU Setup time for GD_SEL pin 50 ns
GATE DRIVER STAGE
IOUTH1 Peak source current CL = 0.22µF 5 A
IOUTH2 Peak source current CL = 0.22µF 10 A
IOUTL1 Peak sink current CL = 0.22µF 5 A
IOUTL2 Peak sink current CL = 0.22µF 10 A
ROUTH1 Output pull-up resistance IOUTH1 = -100mA 0.725 1.35 Ω
ROUTH2 Output pull-up resistance IOUTH2 = -100mA 0.445 0.775 Ω
ROUTL1 Output pull-down resistance IOUTL1 = 100mA 0.725 1.35 Ω
ROUTL2 Output pull-down resistance IOUTL2 = 100mA 0.445 0.775 Ω
ACTIVE PULLDOWN
VOUTPD Output active pull down on OUTLx IOUTLx = 100mA,
VDD=OPEN, VEE=COM		 1.0 1.4 1.85 V
INTERNAL MILLER CLAMP
VCLMPTH Miller clamp threshold voltage Reference to VEE 1.5 2.1 2.5 V
ICLMPI Output low clamp current VCLMPI = 0V, VEE = –4V   4   A
RCLMPI Miller clamp pull down resistance ICLMPI = 0.1A 0.6 1.2 Ω
tDCLMPI Miller clamp ON delay time CL = 1.0nF 33 50 ns
SHORT CIRCUIT CLAMPING
VCLP-OUTH1 VOUTH1 - VDD OUT = Low, IOUTH = 100mA, tCLP=10us 0.8 1.0 V
VCLP-OUTH2 VOUTH2 - VDD OUT = Low, IOUTH = 100mA, tCLP=10us 0.75 1.0 V
VCLP-OUTL1 VOUTL1 - VDD OUT = High, IOUTL = 100mA, tCLP=10us 1.0 1.5 V
VCLP-OUTL2 VOUTL2 - VDD OUT = High, IOUTL = 100mA, tCLP=10us 0.95 1.25 V
DESAT PROTECTION
ICHG Blanking capacitor charge current VDESAT = 2.0V 420 540 580 µA
IDCHG Blanking capacitor discharge current VDESAT = 6.0V 18 20 mA
VDESATTH Detection threshold 8.5 9 9.5 V
tDESATLEB Leading edge blank time 160 200 280 ns
tDESATFIL DESAT deglitch filter 60 125 150 ns
tDESATOFF DESAT propagation delay to OUT 90% VDESAT>VDESATTH 200 300 ns
tDESATFLT DESAT to FLT low delay 1 µs
SOFT SHUTDOWN (SSD)
ISSD Peak sink soft shutdown peak current CL = 0.22µF, fS = 1kHz 2.5 A
RSSD Soft shutdown pull-down resistance ISSD = 0.1A 1 Ω
tSSD Soft shutdown ON time 25 µs
OUTPUT GATE VOLTAGE MONITOR
VGMHI Gate monitor threshold referenced to VDD IN+ = high and IN- = low. -3 V
VGMLO Gate monitor threshold referenced to VEE IN+ = low and IN- = X. 3 V
tGMFIL Deglitch filter on gate monitor 0.9 1.2 1.6 µs
tGMFB OUT to OUT_FB delay 1.7 2.4 µs
VGMFBOL GM_FB output low voltage level IGMFB = 10mA. Reference to GND 245 mV
VGMFBOH GM_FB output high voltage level (offset below VCC) IGMFB = 10mA 0.78 V
ACTIVE SHORT CIRCUIT (ASC)
VASC2L ASC2 input low threshold referenced to COM 1.2 1.45 1.7 V
VASC2H ASC2 input high threshold referenced to COM 2.3 2.7 3.1 V
RASC2D ASC2 input pulldown resistance 100 kΩ
tASC2FIL ASC2 deglitch filter time 400 700 ns
tASC2_r ASC2 on delay to output high 1 µs
tASC2_f ASC2 off delay to output low 1 µs
OVERTEMPERATURE PROTECTION
TTSDTH Thermal shutdown rising threshold 155 185 °C
TTSDHYST Thermal shutdown hysteresis 20 °C
FAULT REPORTING (FLT, RDY)
tRDYHLD UVLO RDY low minimum holding time 0.55 1 ms
tFLTMUTE Output mute time on overcurrent fault Reset fault through RST/EN 0.55 1 ms
RODON Open drain output on resistance IODON = 10mA. Reference to GND 25 Ω
VODL Open drain low output voltage 0.4 V
COMMON MODE TRANSIENT IMMUNITY
CMTI CMTI noise immunity VCM = 1200V 500     V/ns
(1) Currents are positive into and negative out of the specified terminal.
(2) All voltages are referenced to COM unless otherwise noted