UCC35131-Q1 has soft-start mechanism that ensures a smooth and fast soft-start operation with minimum input inrush current. The output voltage soft-start diagram is shown in the figure below. After input voltage is higher than the VIN_UVLO threshold, and the ENA signal is pulled high, the soft-start sequence starts with a primary duty cycle open loop control. The power stage operates with a fixed burst frequency with an incremental increasing duty cycle starting at 6.5%. The rate of change of the duty cycle is pre-programmed in the part to reduce the input inrush current while building the output voltage VDD. The primary side limits the maximum duty cycle to 62.5% during this phase till the secondary side VDD voltage passes VDD_UVLO before releasing this duty cycle limit. This limit will ensure minimum input current in case the device starts on a short circuit and the VDD is not building up. Once the VDD reaches the regulation range, the duty cycle is no longer determined from the primary side controller but instead VDD hysteretic control is active to tightly regulate the output voltage within the defined hysteresis band.

When VDD passes V_{VDD_UVLO}, a FBVEE status check will be performed, and then a single inductor current pulse is generated for BSW pin fault detection. When VDD reaches regulation, the VEE soft start occurs with low peak current. In this way, the charge current of isolated converter can dedicatedly supply VDD cap first before the VEE soft start. The soft start process of VEE voltage has two phases. In phase 1, limited VEE soft start peak current at the beginning reduces the power loss before the soft-start timeout expires, especially when VEE pin is shorted to COM. When V_COM-VEE is higher than V_{VEE_SS} (0.5V Typ.), the VEE soft start enters phase 2, and the inductor peak current is increased to a higher value so that the startup time of charging VEE capacitor will show faster ramp rate.

For the Power-Good signal generation, when VDD voltage reaches regulation, two timers of t_{VEE_SSTO} and t_{PG_Delay} are started. If VEE does not pass VEE_UVP threshold within t_{VEE_SSTO} period, a fault will be triggered to shut down the part and flag a failed soft start. If no fault is detected up within t_{PG_Delay} period, Power-Good signal will change to active status to indicate a Power-Good state. If VDD voltage does not reach regulation within t_SSTO peroid, a fault will be triggered to shut down the part and flag a failed soft start.

Once a fault is triggered to shut down the part, an auto-restart timer of t_RESTART will start afterwords, and the part will attempt to auto-restart after that timer expires. If the fault condition remains, the part will shut down again and attempt another auto-restart. The device can continuously operate safely in hiccup mode as long as the fault occurs.

To ensure VEE reaches VEE_UVP threshold within t_{VEE_SSTO} period, the sum of the COM-to-VEE output capacitance at gate driver side (C_{VEE_GD}) and at isolated-converter bias side (C_{VEE_BIAS}) should not exceed a maximum allowed value. The maximum allowed value at gate driver side (C_{VEE_GD}) is available in a calculation tool, as another design supporting document besides this datasheet. The equation to determine the maximum allowed capacitor value is shown as below, and is implemented in the calculation tool. In the equation, I_{LOAD_SS_VEE} represents the quiescent current of output load during VEE soft start.